Re: gEDA-user: merge multi symbol components

[Gabriel Paubert <paubert@xxxxxxx>]

On Wed, Jul 22, 2009 at 10:55:33AM +0000, Kai-Martin Knaak wrote:
> On Tue, 21 Jul 2009 22:28:37 -0400, DJ Delorie wrote:
> 
> > Note that I have at least one schematic where the merging of the symbols
> > would have duplicated pins; this is intentional and they're supposed to
> > be "connected" together.  
> 
> Just to be sure: The duplicated pins refer to the same physical pin, do 
> they? If this is true, a merge of pin lists would be correct. 
> 
> The main case I'd like to catch is unintentionally duplicated symbols. If 
> both, refdes and all pins are identical, it is safe to assume an error. 

Well, could we use the pintype attribute as a hint? Passive and power
typically might be duplicated. I doubt you will have frequent duplicate 
inputs and/or outputs. (In a typical FPGA design, I might duplicate
the Vref pins for some I/O standards because several symbols share the same
I/O bank, however the inputs and outputs will use different pins).

I might be very wrong on this, however.

	Gabriel


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