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Re: gEDA-user: PCB Lines Over Polygons & Layer-groupings
On the subject of having objects on one layer effect the other layers:
Some devices such as high frequency current feedback opamps (example:
AD8009) have a tendency to peak at the high frequency if their inverting
pin has capacitance associated with it. Even small amounts of parisitic
capacitance could cause these types of devices to occilate. So, all
other copper should be cept away from under them and other pads and
traces wich directly connect to them.
A second example is the impedence characteristics of strip lines. The
impedence changes when you have a copper polygon/trace underneith and
when you have just free space.
I am not advicating having PCB have the capability to do this
automatically. But it is one example of how objects on one layer are
effected by other layers.
Steve Meier
William Dieter wrote:
On Tue, 15 Jun 2004 09:33:11 +0200, Levente KOVACS <leva@interware.hu> wrote:
On Mon, 14 Jun 2004 17:22:09 -0400
William Dieter <william.dieter@gmail.com> wrote:
Is there any way to add clearance for lines in the same layer group as
polygons, but in different layers? I am using pcb-20040530.
I think that does not makes so much sence. Imagine, that you have 2
layer board. You have a line at the top layer, and a ground plane at the
bottom. Why should the botom layer cleard?
That's not what I want to do. I agree that if they layers are
physically different, a line should not clear polygons in other
layers. However, pcb allows layers to be grouped, so that logically
separate traces can be put in different "layers" even though layers in
the same group are put into the same physical layer on the board. The
reason for grouping layers is to make it easy to distinguish between
traces in the same layer (for example, if you have Vcc and GND traces
on the same layer as signals.)
By default, pcb has three layers "solder", "GNC-sldr", and "Vcc-sldr"
that are grouped together in the same physical layer on the board.
There are three similarly grouped layers on the component side as
well. If a trace in the Vcc-sldr layer overlaps a trace in the
GND-sldr layer they will be shorted together in the final design.
I am designing a two layer board and the component layer is mostly
ground, but I need to use the component layer to route a few signal
traces. I could put the signal traces and the ground into the same
layer and get the line-clearing effect I want. The layout looks nicer
and is easier to understand if the ground is in the GND-comp layer and
the signal traces are in the component layer, but pcb doesn't create
any clearance around the signal traces. I would have to manually
carve out behind all the traces prevent the traces from being shorted
to ground.
Bill.