This one is not too hard:
1) Create a bunch of separate symbols, one for each sub-function, bank, power, whatever. Name them in such a way that you can associate them together. eg. cpu-1.sym, cpu-2.sym, cpu-3.sym, etc.
2) Put one copy of each of them onto the schematic. Give them all the same refdes attribute. eg. if your big part is `U1', attach `refdes=U1' to all of the symbols.
3) Netlist the design. Understand that gnetlist indexes the components by the value stored in the `refdes' attribute. What happens under the hood is that all of the components on a schematic labled with the same `refdes' get _merged_ into one giant component. This applies for the attached attributes as well, so that is why you only have to add `footprint' et al. to one of the symbols.
You may want to be careful about running the refdes renumbering scripts included in the gschem distro as I don't know if they handle heterogenous components like this correctly. You may wind up with several unique reference designators and several footprints on the layout.
Mike
"Samuel A. Falvo II" wrote:
On 6/26/05, Andy Fong <boringuy@xxxxxxxxx> wrote:
> I don't quit unterstand. The refdes in the symbol file now is set to U?.
> Are you saying just use the same refdes for the schematic(eg. U1 for
> all symbols)?
> You said give one of them a value and footprint. What value are you refering to?In the symbol file, refdes is set to U?. In the actual schematic,
you'll want to change it to a consistent value.For example, when placing four gates of a 7400 chip, each will appear
in the schematic as having 3 pins (1, 2, and 3), and U? as the refdes.
Changing the 2nd, 3rd, and 4th item to U1 (assuming the first is also
U1), then editing the "slot" attribute will reveal the subsequent
slots. That will adjust pin numbers and the like.What I personally don't get is how to have different *shapes* for the
different slots. For example, suppose I make a CPU part with hidden
power. The first slot would be the 38-or-so pins that I'd need to
connect address, control, and data buses with. Then slot 2 would just
be Vss and Vdd. THAT is what I personally don't know how to do yet
(although, admittedly, I haven't really had a need for that just yet).--
Samuel A. Falvo II
-- -------------------------------------------------- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek --------------------------------------------------