Re: gEDA-user: SPICE/gEDA updated. . . . .

[mcmahill@mtl.mit.edu]

As a more concrete example, suppose you have a standard CMOS process.  You
may have only 2 models for transistors.  One is NMOS and one is PMOS.  If
you take a look at the line in a spice netlist for say the nmos
transistor, it looks something like:

M1 drain_node gate_node source_node bulk_node model_name list_of_parameters

This may look like:

M1 2 1 0 0 nmos W=100u L=0.6u

in its most basic form where W and L are gate width and length.  So far,
we can get by with a simple .include statement to pull in a model file for
the process which would include a nmos model (plus probably a pmos model
and perhaps some resistor and capacitor models).


However to properly model the diode formed by the source/drain diffusions
and the substrate, you also need to specify the AS, AD, PS, PD parameters.  
Now your FET call looks more like:

M1 2 1 0 0 nmos W=100u L=0.6u AS=200p AD=200p PS=204u PD=204u

where the exact calculation of what AS, AD, PS, and PD is based on 

- what are W and L
- how many fingers used in the device (you wouldn't make a 100u x 0.6u
  rectangle but would break this into perhaps 10 rectangles which are 10u
  x 0.6u)
- what is the minimum gate to contact spacing
- what is the contact size
- what is the minimum amount the diffusions must enclose contacts by.

So in practice what happens with a tool such as cadence, a process design
kit has been developed so that when you enter W and L for a device, the
tool calculates what AS, AD, PS, and PD will be so that when the netlist
is created for simulation, those values (fully evaluated, ie, the
netlist doesn't have equations but rather the outputs of equations) are
included in the netlist.

To summarize, for IC work, you typically have both a model file which gets
included somehow and some other technology specific setup which affects
how a schematic gets netlisted including doing things like calculating
additional parameters from a set of specfied parameters.

Hope this clarifies things a little bit.

Now, with regards to a flat netlist vs a hierarchical netlist, I think its
extremely useful to have both available.  A flat netlist is required if
you want to do stuff like include a set of parasitic capacitances
extracted from a layout.  You need a flat netlist for this because you may
have coupling between internal nodes of 2 different subcircuits.  On the
other hand, with a hierarchical netlist, you have the ability to easily do
things like use awk to delete the subcircuit definition for a particular
block and replace it with an include of a macromodel.  For example, maybe
on a board level schematic you have a filter consisting of several op-amps
and associated components.  For some sims you may wish to delete the more
complete model and substitute a simpler model made of a couple of voltage
controlled voltage sources and a simpler LC filter.  This could reduce sim
times when you're focusing on some other aspect of the larger circuit.

-Dan


On Sat, 22 Mar 2003, Stuart Brorson wrote:

> I'm a board designer, not a chip guy, so I may be on shakey ground
> here.  Please allow me to ask a couple of questions.
> 
> 1.  First off, what kind of netlist are you interested in?  If it's a
> SPICE netlist, can you just use a .INCLUDE card?  If so, there is a
> .INCLUDE block symbol which you can stick into your schematic. This
> symbol lives in the SPICE symbols which are included in the standard
> gEDA dist, and which I have augmented & made available on my web site.
> 
> BTW: Both of the examples I put on the web incorporate a .INCLUDE
> symbol as a way to incorporate SPICE analysis commands in the
> schematic, so you can take a look at them. 
> 
> 2.  If it's more than just an .INCLUDE, does standard, vanilla SPICE
> have a corresponding card?  How do you get the equations into a SPICE
> netlist?  
> 
> 3.  Hmmm. . .   As I consider it, I guess that the answer to your
> question depends upon how you incorporate the technology file into
> your netlist.  Here are some options: 
> 
>   *  If your final product is a flat netlist with a reference to your
>   technolog file in it (like  #include "technologyfile.h" statement in
>   c), then you can easily put a corresponding "include" symbol in your
>   schematic.   
> 
>   *  If you want to actually put the statements in the flat
>   netlist, then you can place a pointer to teh technology file into a
>   .MODEL block symbol.  Upon netlisting, the contents of the file will
>   be read from the file and placed in the netlist itself.
> 
>   *  If it's something more subtle (like setting an
>   environmental variable), then putting it in the .rc may be better. 
> 
> Do you have an example?
> 
> Stuart
> 
> 
> > cool stuff.  I'll be checking it out tonight.  One thing I've been
> > wondering about is how one might have some hooks for a technology file if
> > you wanted to use gEDA for IC type schematics.  Where you care about this
> > is the following:  
> > 
> > You're doing a MOS transistor design.  For a given technology, you can
> > calculate the AS, AD, PS, PD parameters (source and drain areas and
> > perimeters) from the specified width, length, and number of fingers for
> > the device.  The commercial tools all provide hooks so that the tool will
> > properly fill in those parameters in your netlist based on some equations
> > that include process dependent parameters.  I've been wondering what it
> > would take to get such a hook into gEDA.  It seems like a good way might
> > be to have a line in the gnetlistrc file for the project that specified a
> > particular technology library.  Then you'd just want to figure out how to
> > have the netlister provide some sort of hook where you could insert
> > whatever extra equations you may need.
> > 
> > Anyway, I'll be anxious to see what you've done with the spice netlister.
> > I've been thinking of doing a switcap backend so I imagine there may be
> > something for me to learn from your work.
> > 
> > -Dan
> > 
> > On Sat, 22 Mar 2003, Stuart Brorson wrote:
> > 
> > > Greetings gEDA gurus,
> > > 
> > > I've been hacking on my SPICE netlister more, and now have
> > > incorporated the ability to use .SUBCKT model files into the
> > > netlister, as well as improved things in other ways.  I have posted my
> > > stuff on my "SPICE on gEDA" web page: 
> > > 
> > > http://www.brorson.com/gEDA/SPICE/
> > > 
> > > There, you will find the following:
> > > 
> > > *  Updated SPICE on gEDA HOWTO 
> > > *  gnet-spice-SDB.scm -- the new and improved Scheme back end
> > > *  Some spice models from LT and Analog Devices
> > > *  Two projects which I have built and simulated using LTSpice
> > > *  Other good stuff
> > > 
> > > If you are interested in using gEDA schematic capture & netlisting
> > > tools as a SPICE front end you may be interested in checking it out.
> > > 
> > > Comments and suggestins are welcome!
> > > 
> > > Stuart
> > > 
> > 
> > 
>