Re: gEDA-user: iverilog synthesis

[温宇杰 <yujie.wen@xxxxxxxxxxxxxxxx>]

Hello, Patrick,

I just starts re-targeting iverilog to some of our own FPGA fabrics. I
am still learning the iverilog codes. But, ff you are worrying about
generating netlist for your structure, iverilog has provided an
interface called ivl for you to manipulate logic gates and computing
units like adders, subtracters and more. You can learn the concept of
ivl by reading "ivl_target.h" and "t-dll.h". Usually, what you need to
do is compiling you netlist generation codes into a shared object or DLL
for windows platform. iverilog will call target_design() of your .so and
you can call many ivl_* routines to gather necessary information within
target_design() and write out your own netlist. The codes in
sub-directory tgt-fpga and other tgt-* are also good references for you.
Hope they can help you.

Best regards.
Yujie Wen

Patrick Doyle 写道:
>    Would somebody point me in the right direction for learning more about
>    synthesis with Icarus Verilog?  I'm happy to read the source, but
>    synth.cc doesn't seem like the right place to start.
>    Specifically, I am curious to learn if anybody has used Icarus Verilog
>    to target a custom ASIC design.  I am fascinated by the concept of
>    doing something like this, and would like to learn if and how it could
>    be done.
>    At the highest level, I can appreciate using Icarus Verilog for an
>    FPGA target, where one somehow tells iverilog about the capabilites of
>    a CLB/slice and, based on that information, iverilog would know how to
>    fill in the LUT and how to configure the flop, but I am very curious
>    to learn how one might tell iverilog about some set of primitives
>    (possibly as primitive as NAND, NOR, NOT, and D-flip-flop) and it
>    would somehow be able to synthesize a netlist for wiring those
>    together to match the verilog model.
>    But aside from the philosophical discussion of how one does this sort
>    of thing, I don't even know were to start to read some documentation
>    about how one might target, for instance, a specific FPGA.  I have
>    seen a few references on this list to folks writing their own backend
>    target -- where did they go to learn what they needed to know?  So I
>    am also curious about the nuts & bolts and don't know where to turn.
>    Thanks for any pointers you might care to toss at me...
>    --wpd
>    --wpd
>
>   
> ------------------------------------------------------------------------
>
>
>
> _______________________________________________
> geda-user mailing list
> geda-user@xxxxxxxxxxxxxx
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
>   




_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user