gEDA-user: iverilog synthesis

[Patrick Doyle <wpdster@xxxxxxxxx>]

   Would somebody point me in the right direction for learning more about
   synthesis with Icarus Verilog?  I'm happy to read the source, but
   synth.cc doesn't seem like the right place to start.
   Specifically, I am curious to learn if anybody has used Icarus Verilog
   to target a custom ASIC design.  I am fascinated by the concept of
   doing something like this, and would like to learn if and how it could
   be done.
   At the highest level, I can appreciate using Icarus Verilog for an
   FPGA target, where one somehow tells iverilog about the capabilites of
   a CLB/slice and, based on that information, iverilog would know how to
   fill in the LUT and how to configure the flop, but I am very curious
   to learn how one might tell iverilog about some set of primitives
   (possibly as primitive as NAND, NOR, NOT, and D-flip-flop) and it
   would somehow be able to synthesize a netlist for wiring those
   together to match the verilog model.
   But aside from the philosophical discussion of how one does this sort
   of thing, I don't even know were to start to read some documentation
   about how one might target, for instance, a specific FPGA.  I have
   seen a few references on this list to folks writing their own backend
   target -- where did they go to learn what they needed to know?  So I
   am also curious about the nuts & bolts and don't know where to turn.
   Thanks for any pointers you might care to toss at me...
   --wpd
   --wpd


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