Re: gEDA-user: DRC UI mockup

[Steven Michalske <smichalske@xxxxxxxxx>]

On Mar 29, 2009, at 1:29 PM, DJ Delorie wrote:

> + drill too small (5)
> + annular ring too small (18)
> - copper areas too close
>  + 5.0 mil line/pin at 12500,7500
>  + 4.8 mil line/pin at 11500,8500
>  + 5.0 mil line/pin at 10500,3250
> + silk over pads (1)


I like this but I suggest a different grouping for drill too small and  
annular ring too small.

Often vias get placed that violates rules.  we put 100 of them down

25 that are 10mil hole and 26 mil size, this stack violates say a  
drill too small ( 15 mil min )
50 that are 25 mil hole and 36 mil size, this stack violates min  
annular ring. ( 10 mil min )
25 that are 8 mil hole and 20 mil size, this stack violates drill too  
small and min annular ring.

This presents two DRC errors that are already separate clusters, it's  
the via stack that violates the rules  not each and every via....
The reason for this is in design we usually stick to a few via  
selections.

so as I see it.


+ Via violations
	10 mil by 36 mil via violates drill too small ( 25 )
	25 mil by 36 mil via violates min annular ring. ( 50 )
	8 mil by 20 mil via violates drill too small and min annular ring  
( 25 )
+ Pin violations
	......

when you get details on those via clusters  some fixing options should  
be made available.

with the DRC rules we know the minimum via sizes,  15 mil hole and 35  
mil size.

for the first error we just need to adjust the drill bigger.
	This should not cause any issues, nice easy fix.
The second error should recommend that we shrink the drill, this would  
not break layout rules, but could cause electrical violations.
	This should be logged to a DRC violations and corrective action file.
The third error we need to bump up the min drill and then the via size  
to make the vias DRC compliant.
	This will undoubtedly cause vias to break other DRC rules,  but the  
drills are a big limiting factor, before going to say laser drills.
	This type of error suggests that we need a higher tech process for  
this board.

Similar errors will occur on pins, similar resolutions could apply,   
but the question I ask here is should we fix the footprint or just fix  
the layout?




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