Re: gEDA-user: General Layers questions

[Stephan Boettcher <boettcher@xxxxxxxxxxxxxxxxxx>]

Steven Michalske <smichalske@xxxxxxxxx> writes:

> On Fri, Mar 18, 2011 at 12:40 PM, Martin Kupec <martin.kupec@xxxxxxxxx> wrote:
>> On Wed, Mar 16, 2011 at 10:36:24AM -0600, John Doty wrote:
>>>
>>> On Mar 16, 2011, at 4:24 AM, Stephan Boettcher wrote:
>>>
>>> >> Ok. So "via" should be a circle element on "hole" typed layer.
>>> >
>>> > No. ÂA Via is a composit, consisting of a circle on the hole layer, and
>>> > various circles on copper layers, and circles on mask layes, and
>>> > thermals.
>>>
>>> The "layer" concept should be physical, not a metaphysical abstraction. Objects in a layer may contain holes, but a "hole layer" is nonsensical, a toxic conceptual shortcut. An "outline" layer is similarly bad: the insulating layers may all have the same shape sometimes, but not always.
>>
>> The outline layer will be part of 'physical' layer. So if you have 2
>> 'physical' layers with different shape, it will play nicely.
>>
>> What I am prosposing is 2 level concept. There will be 'physical'
>> layers, so you can add properties to them. And than there will be
>> 'drawing' surfaces. And 'outline' is just drawing suface telling the
>> 'physical' layer it's edges.
>>
>> But I am not convinced that we need special 'hole' typed layer. Maybe we
>> can things like 'holes' which are not part of any specific layer just
>> float in space. I thing that it would work.
>>>
>>> Trying to model things that aren't layers as if they were layers is one common mistake in this kind of tool. Equally common is leaving out layers: the insulating layers in a PCB are just as important as the copper, and have their own properties (shape, thickness, material, etc.). They're a critical part of the layer stack.
>>
>> The problem I see with the insulating layers is that there is nothing on
>> them...So you don't need them as 'drawing' layers. But I agree that
>> there should be a way how to add some attributes to them.
>
>
> Embedded resistor and capacitors are in holes in the separating layers.
>
> Some separating layers are more like a solder mask and sprayed down
> rather than FR4 and prepreg.
>
> Just because standard FR4 Fabs don't usually use any drawings on that
> layer, should not preclude it.
>
> Now the exporter may barf if it finds something it can't cope with,
> like a line drawn on a separator layer.

If you have a foundry that does such things, probably you send them a
gerber layer and tell them that those are the embedded resistors between
copper 2 and 3.  And that other layer are those between copper 5 and 6.

No special exporter required.  But you must keep the drawing layers a
bit more abstract, else you confuse the tools that have invalid
assumptions.

The embedded resitors will be elements in a process specific library.
Not top/inner/bottom layers, that get mapped to the layer present in the
layout, but footprints with explicit layers.  Including a shape on the
resistive layer, and pads on the adjacent copper layers.

The pcb layout tool will not need to know anything about those embedded
devices.  They just emerge and work.  All you need is layers that are
not marked conductive.

And if those strange embedded deviced become common, somebody needs to
add some DRC rules, which at that time are just a few boolean ops on some
layers in a config file.

-- 
Stephan


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