Re: gEDA-user: fritzing

[Eric Brombaugh <ebrombaugh1@xxxxxxx>]

Ben Jackson wrote:
>> The only way these things are at all possible is with a wide variation 
>> in levels of abstraction. They guy designing the transistors doesn't 
>> know about the circuits they go into, while the architect working on the 
>> memory management can't be bothered with the ESD structures of the I/O 
>> pads.
> 
> That's all true.  I just don't think it goes far enough.  I don't know
> if that's because it's a Hard Problem or if it's because engineers have
> expectations that are too low.  As a software engineer I came to the
> party with much higher expectations.

I'd argue that's it's a bit of both - it's a hard problem and we don't 
have the option of holding our breath until someone gives us the 
high-level tools. And it's not because no one is trying either - if you 
look at the research that has gone into creating the tools we have today 
you'd agree that it's not just due to laziness or 'make do'. It's like 
speech recognition or image processing - things that a trained person 
can do fairly easily but are very difficult to implement in machines.

> I would compare the current state of FPGA development tools with my early
> 8-bit computer experience.  On my Commodore 64 I cared about every memory
> location on the system.  I wrote anything remotely important by hand in
> assembly.  Writing Verilog is at the abstraction level of approximately
> a macro assembler.  At the high end it might reach up into the level of
> BASIC.

No arguments here. OTOH, if you actually look at what's going on inside 
of an HDL synthesis tool as it turns your RTL into gates, I think you'd 
see that it's at least as complex as what a good optimizing C compiler 
is doing. It's just that the syntactic difference between the ideal HDL 
you'd like to use and hardware gates is a lot greater than that between 
C and machine code (which probably tells you something about C ;) )

Eric




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