Re: gEDA-user: Two things ... or actually, three

[Stephen Ecob <silicon.on.inspiration@xxxxxxxxx>]

On Tue, May 31, 2011 at 7:21 AM, Richard Rasker <rasker@xxxxxxxxxx> wrote:
> Op donderdag 26-05-2011 om 22:56 uur [tijdzone +1000], schreef Stephen
> Ecob:
>> > Then two more usage questions:
>> > - Zero length lines in PCB: I found that when drawing lines in PCB,
>> > sometimes dots (zero length lines) get created inadvertently on corners
>> > and bends. This isn't much of a problem, until I start dragging lines
>> > and end points in rubber band mode: those dots then get stretched into
>> > undesired line segments which I sometimes don't notice until I get DRC
>> > errors and warnings about short circuits.
>> > Do I recall correctly that someone created a script to filter out those
>> > zero-length lines? I can't find anything in the mailing list archives,
>> > and it turns out that a regex recognizing Line[X Y X Y ... ] doesn't
>> > seem all that trivial to construct.
>>
>> These *may* be fixed up by "Connects -> Optimize routed tracks ->
>> simple optimization". ÂUse this feature with care - it usually removes
>> zero length lines but occasionally it also erases needed trace
>> segments by mistake. ÂI recommend saving first and performing DRC
>> check and net connectivity check ("o" key) both before and after,
>> checking for any changes - there /should/ be none.
>>
>> The trace optimizer only touches autorouted tracks by default - if you
>> want it to work on manually routed traces you need to clear the
>> "Connects -> Optimize routed tracks -> [/] Only autorouted nets"
>> checkbox.
>
> ïThanks for the suggestion, but it messed up the layout something
> wicked: over a 100 short circuits in my 1800+ nets. I'd prefer a simple
> script to weed out lines of 0 and 1 mil length, and I don't mind writing
> it myself if necessary.
>
> Anyway, thanks again, best regards,
>
> Richard Rasker

Oh sorry, we're writing emails at the same time!

You could consider making a stripped down version of "Connects ->
Optimize routed tracks -> simple optimization".  Part of if removes
microlines.  The code is in pcb/src/djopt.c around line 1200.  Look
for the text "LONGEST_FRECKLE"


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user