Re: gEDA-user: How to deal with single/dual parts?

[Greg Cunningham <greg@xxxxxxxxxxxxxxxxxxxx>]

> Peter Clifton wrote:
> > Lets say I have a symbol:
> >     ____
> > ---|    \____
> > ---|____/
> >
> >
> > That might have 4 slots - IE.. I expect 4 of those nand gates in the
> > chip.
> >   
> 
...
If you are willing to entertain the thoughts of a lurker...

I used to repair those old discrete logic arcade amusement machines -
from 100% ttl up to when they adopted 16-bit cpus.  

Lets say we wanted to design something similar, say a 500-gate design to
be implemented in LSI/MSI. As Stefan has said, this must be 100%
conceptual.  Forcing me to assign gates to devices at any time except
layout will be a great handicap.  There will be __many__ times that the
track layout will decide which gate lives inside which IC. 

What would be nice here is a loose coupling between symbol and device to
the extent that symbols could be dynamically assigned to devices.  Maybe
there could be a 'devices' panel (maybe even the assigned list from the
library).  Each device in the panel exposes its used and available
slots.  The designer can form a symbol-device association by dragging
the symbol onto a suitable device in the device panel to 'assign' the
symbol to an available slot.  The drop fails if the symbol doesn't fit
the device, or if all slots for that symbol are taken.  Also, I could
merely drag the symbol out of one devices slot and drop it in another
device that gives me better routing efficiency. 

-- 
Greg Cunningham <greg@xxxxxxxxxxxxxxxxxxxx>



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