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Re: gEDA-user: pcb outline clarification
On Mon, 2010-10-25 at 17:53 +0200, Stefan Salewski wrote:
> On Mon, 2010-10-25 at 17:20 +0200, Markus Hitter wrote:
> > Am Montag, den 25.10.2010, 12:53 +0200 schrieb Markus Hitter:
>
> >
> > Looks like coding simplification is favoured over user friendliness. OK,
> > scratch that idea of a patch.
applying "s/strcmp/strcasecmp/" is no more simple than what we have now,
just not something we considered desirable when reflecting upon it.
Currently "outline" and "route" have special meaning, and any layer
witih that name is treated differently when exporting. Existing users
will have boards with these layer names (assuming they are relying on
the special handling).
If we add more "magic" layer names, either by strcasecmp, or introducing
more synonyms, special handling for "mechanical" / "notes" / whatever..
we risk breaking boards of users who might inadvertently have used those
names for non-special things.
Whilst I grant you that the risk of damage is probably low, with CAD
tools it is generally very important not to have a new version of the
tool change fundamental handling of old design files. This might mean
complicating the code to make the new layer names active only for new
files.
[snip]
> For the layer stuff my impression was, that some of the developers
> intend a complete rewrite, so that we can have multiple layers of each
> type, new types like keepouts, and maybe routing styles and DRC
> specification bound direct to layers. My impression may be wrong, I am
> not involved in current PCB development.
The layer types work has been planned for quite a while now. The
intention is to remove all special casing based on layer name
(internally at least), and make the handling based on layer attributes /
flags. We would of course retain code to auto-apply the appropriate
flags to old boards which feature the old special-cased names.
I don't have any idea when the new functionality will appear, and I'm
not working on it myself. My only involvement before was to clear up the
ambiguity where some pieces of code accepted layer names case
insensitively and others did not.
Regards,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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