Re: gEDA-user: GND and Vcc pin on IC 74245

[Stephen Meier <smeier@xxxxxxxxxxxxxxxxxxx>]

GAF does allow symbols to have pins for the power connections or to have 
the power connections as hidden nets.

The problem often is is what voltage is Vcc or Vdd.

Why not make the symbols have a +5v or a +3.3v power net?

What about devices that Vcc could be any value .. say less then 12 
Volts? For these we need a way to assign the values. We could have 
multiple symbols. We could use expossed pins there are a number of 
solutions available in gaf. I would prefer to have only 2 sets of 
symbols one which uses hidden nets that can be over ridden by an 
attribute and one set with expossed pins.

(point for discussion --- should this be on the developer list?)

This is where an attribute for Vcc for a device where the user could set 
the voltage (the net) might be a solution.

But.... on a lot of the high speed analog circuits I like to put an 
inductor followed by three capacitors before I connect to the power pin 
of the device.... using an over ride attribute would require me to name 
a lot of nets that I don't want to name. ok well for those devices I 
just put a pin for each of the power pins... 

See the attached symbol for an Analog Devices AD8009 is an SO8 package. 
Pins 4 and 7 are the power pins. This is a 1 Ghz current feed back 
opamp. It is very important to filter the power going into pins 4 and 7. 
My point is gaf doesnt care to gaf a net is a net. Note that there are 
no hidden nets for power or ground.

Cheers,

Steve Meier





Ales Hvezda wrote:

> > Could someone explain why logic ICs must not have Vcc and GND pins?
> > I have never seen a good reason for this. What is wrong with having 
> > Vcc and GND pins - like any other pin?
> >
> >    
>
> 	In gEDA/gaf, ICs can have explicit power pins.	The fact that
> they do not is just the way the gaf symbol library has evolved.
> Some people like it, other absolutely hate it.	So, that's why it's very
> easy to create new parts which have the "right" features according to
> the beholder. :)  This discussion is unfortunately religious.
>
> 								-Ales
>
>
>  

v 20040111 1
L 200 800 200 0 3 0 0 0 -1 -1
L 800 400 200 800 3 0 0 0 -1 -1
P 200 600 0 600 1 0 1
{
T 50 625 5 8 1 1 0 0 1
pinnumber=3
T -450 725 5 8 0 0 0 0 1
pinseq=3
T 200 600 5 7 1 1 0 0 1
pinlabel=+IN
T 200 600 5 10 0 1 0 0 1
pintype=in
}
P 200 200 0 200 1 0 1
{
T 50 225 5 8 1 1 0 0 1
pinnumber=2
T -550 225 5 8 0 0 0 0 1
pinseq=2
T 200 200 5 7 1 1 0 0 1
pinlabel=-IN
T 200 200 5 10 0 1 0 0 1
pintype=in
}
P 800 400 1000 400 1 0 1
{
T 875 425 5 8 1 1 0 0 1
pinnumber=6
T 875 525 5 8 0 0 0 0 1
pinseq=6
}
P 500 600 500 800 1 0 1
{
T 550 675 5 8 1 1 0 0 1
pinnumber=7
T 550 875 5 8 0 0 0 0 1
pinseq=7
T 400 450 5 7 1 1 0 0 1
pinlabel=+VS
T 550 600 5 10 0 1 0 0 1
pintype=in
}
P 500 200 500 0 1 0 1
{
T 525 50 5 8 1 1 0 0 1
pinnumber=4
T 525 -50 5 8 0 0 0 0 1
pinseq=4
T 400 250 5 7 1 1 0 0 1
pinlabel=-VS
T 550 150 5 10 0 1 0 0 1
pintype=in
}
L 800 400 200 0 3 0 0 0 -1 -1
T 875 1550 5 8 0 0 0 0 1
footprint=SO8
T 875 1400 5 8 0 0 0 0 1
device=AD8009
T 900 1700 5 8 0 0 0 0 1
slot=1
T 850 1825 5 8 0 0 0 0 1
numslots=1
T 725 650 9 8 1 0 0 0 1
AD8009
T 200 900 8 10 1 1 0 0 1
refdes=U?
T 875 1250 5 8 0 0 0 0 1
documentation=http://www.analog.com/Analog_Root/productPage/pdbPage/