On Friday 09 September 2005 23:45, David D. Hagood wrote:
Wilbert Knol wrote:
Idea and I have always been totally intrigued why anyone would
want to do this - I have yet to see a single, good argument in
favour.
OK, try this - there is not always a one-to-one mapping from
entities on the schematic to ICs. Consider a 7400 quad NAND gate
chip: this part is not rendered as a box with 4 NANDs in it, but as
four separate NAND gates "floating around" on the schematic. OK,
so, where do you put the power pins?
1) On every device, and have the problem of somebody connecting
U1A's Vcc to the +5 digital net, and U1B's Vcc to the +5 analog
net?
Agreed. Unworkable.
2) On one device in the package? Now one device is "special"
and has extra pins, so you cannot auto-number them.
Again, I agree.
Incidentally, this is why the argument that 'gschem allows you to have
a choice' doesn't wash. There is no workable alternative to hidden
power nets.
3) On a hidden net so that the normal behavior is that the parts
"Just Work".
I agree - when you are dealing with a device for which there is a
one-to-one mapping between schematic and board hidden nets are not
really needed, but for some devices they really do make things
cleaner.
This is stating two bad alternatives to (somehow) justify an even
worse solution - see my previous posting why I strongly dislike
hidden nets.
Suggestions:
1. Have the power pins show up only on a virtual, extra gate, or even
just a box to symbolise the package.
2. Or make them show up only on the slot (gate) of one's choice, and
attach an attribute to the gate. This attribute - a list, similar to
the present 'slotdef' attribute - exempts the power pins from being
auto-numbered, and identifies them as being unique to this slot.
Anyway, this is a minor gripe. Gschem is still a great tool.
Wilbert.