Re: gEDA-user: Color silk layers in pcb

[Pawel Kusmierski <drab.odr@xxxxxxxxx>]

On Fri, Sep 3, 2010 at 1:51 PM, Stefan Salewski <mail@xxxxxxxxxxxx> wrote:
> On Fri, 2010-09-03 at 11:53 +0200, Pawel Kusmierski wrote:
> > Dear fellow GEDA-users,
> >    Can I get pcb to either treat a layer other than the default silk as
> >    non-metal
> >    (so it would not short pads and mess up nets),
> Please note, your SUBJECT may be misleading...
>
> No, currently we have only one silk layer. You may "miss-use" other
> copper layers for that task -- it may work when that layer is not in
> your real copper layer groups, but unfortunately it still connects to
> vias and can generate shorts. I did that for visual marks, distinct from
> other silk marks, and I copy that layer to silk before gerber
> production. (Some of us hope that sometimes we will have general propose
> layers, so that we can select type and other parameters separate...)
>
Thanks for your answer Stefan.
I have my visual marks just over vias, and it shorts them together,
so I will look for some other solution.

Is anybody willing to elaborate on how difficult would it be
to modify the pcb source code to color-differentiate three or four
silk layers and be able to selectively hide/show them?

Kind regards,
-- 
Pawel Kusmierski


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