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gEDA-user: Strange user interface behavior with gschem-1.6.2.20110115

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Subject: gEDA-user: Strange user interface behavior with gschem-1.6.2.20110115
From: Josef Wolf <jw@xxxxxxxxxxxxx>
Date: Sun, 4 Sep 2011 22:22:11 +0200
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User-agent: Mutt/1.5.20 (2009-06-14)

Hello,

I have a strange usability behavior with gschem 1.6.2.20110115 (the version
that comes with ubuntu-11.04). I have attached a small schematic to
illustrate the problem.

In the attached schmatic, when I try to draw a net from U6-pin27 to the
gate of Q6, a little circle appears on the nearest pin, indicating where
the connection would be "autocompleted" to. But even if the circle appears
at the gate of Q6, at the moment I click to make the connection, it jumps
to the gate of Q4, effectively shortening pin1 with pin28 of U6.

I have not seen such behavior before. In fact, I have not seen such an
autocompletion-circle before. Is this some new functionality? Is there a
way to deactivate it? Or at least configure it to behave in a sane way?

In the attached file, I have embedded the parts to make sure that whoever
tries to reproduce, gets the identical parts.

Any ideas? Suggestions?

v 20110115 2
C 40000 40000 0 0 0 title-A2.sym
C 40800 46100 1 0 0 EMBEDDEDATmega8-1.sym
[
T 40900 51700 8 10 0 0 0 0 1
device=ATmega8
T 43000 49850 5 10 0 1 0 6 1
net=GND:8,22
T 42700 50050 5 10 0 1 0 6 1
net=Vcc:7
T 42700 50700 8 10 0 1 0 6 1
numslots=0
T 43100 50700 8 10 0 1 0 6 1
refdes=U5
T 40900 50900 8 10 0 0 0 0 1
footprint=DIP28N
T 40900 51300 8 10 0 0 0 0 1
documentation=http://rocky.digikey.com/WebLib/Atmel/Web Data/ATmeg8(L) Preliminary Complete.pdf
T 40900 51100 8 10 0 0 0 0 1
description=Low-power AVR 8-bit Microcontroller
T 43000 50400 9 10 1 0 0 6 1
ATmega8
T 40900 51500 8 10 0 0 0 0 1
Copyright Mark Salyzyn
B 41100 46200 2000 4400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 43100 48400 43400 48400 1 0 1
{
T 43200 48450 5 8 1 1 0 0 1
pinnumber=28
T 43200 48550 5 8 0 1 0 2 1
pinseq=28
T 43050 48400 9 8 1 1 0 6 1
pinlabel=(ADC5/SCL) PC5
T 43050 48400 5 8 0 1 0 8 1
pintype=io
}
P 43100 48600 43400 48600 1 0 1
{
T 43200 48650 5 8 1 1 0 0 1
pinnumber=27
T 43200 48750 5 8 0 1 0 2 1
pinseq=27
T 43050 48600 9 8 1 1 0 6 1
pinlabel=(ADC4/SDA) PC4
T 43050 48600 5 8 0 1 0 8 1
pintype=io
}
P 43100 48800 43400 48800 1 0 1
{
T 43200 48850 5 8 1 1 0 0 1
pinnumber=26
T 43200 48950 5 8 0 1 0 2 1
pinseq=26
T 43050 48800 9 8 1 1 0 6 1
pinlabel=(ADC3) PC3
T 43050 48800 5 8 0 1 0 8 1
pintype=io
}
P 43100 49000 43400 49000 1 0 1
{
T 43200 49050 5 8 1 1 0 0 1
pinnumber=25
T 43200 49150 5 8 0 1 0 2 1
pinseq=25
T 43050 49000 9 8 1 1 0 6 1
pinlabel=(ADC2) PC2
T 43050 49000 5 8 0 1 0 8 1
pintype=io
}
P 43100 49200 43400 49200 1 0 1
{
T 43200 49250 5 8 1 1 0 0 1
pinnumber=24
T 43200 49350 5 8 0 1 0 2 1
pinseq=24
T 43050 49200 9 8 1 1 0 6 1
pinlabel=(ADC1) PC1
T 43050 49200 5 8 0 1 0 8 1
pintype=io
}
P 43100 49400 43400 49400 1 0 1
{
T 43200 49450 5 8 1 1 0 0 1
pinnumber=23
T 43200 49550 5 8 0 1 0 2 1
pinseq=23
T 43050 49400 9 8 1 1 0 6 1
pinlabel=(ADC0) PC0
T 43050 49400 5 8 0 1 0 8 1
pintype=io
}
P 43100 47400 43400 47400 1 0 1
{
T 43200 47450 5 8 1 1 0 0 1
pinnumber=21
T 43200 47550 5 8 0 1 0 2 1
pinseq=21
T 43050 47400 9 8 1 1 0 6 1
pinlabel=AREF
T 43050 47400 5 8 0 1 0 8 1
pintype=in
}
P 43100 47100 43400 47100 1 0 1
{
T 43200 47150 5 8 1 1 0 0 1
pinnumber=20
T 43200 47250 5 8 0 1 0 2 1
pinseq=20
T 43050 47100 9 8 1 1 0 6 1
pinlabel=AVCC
T 43050 47100 5 8 0 1 0 8 1
pintype=in
}
P 41100 46700 40800 46700 1 0 1
{
T 41000 46750 5 8 1 1 0 6 1
pinnumber=19
T 41000 46850 5 8 0 1 0 8 1
pinseq=19
T 41150 46700 9 8 1 1 0 0 1
pinlabel=PB5 (SCK)
T 41150 46700 5 8 0 1 0 2 1
pintype=io
}
P 41100 46900 40800 46900 1 0 1
{
T 41000 46950 5 8 1 1 0 6 1
pinnumber=18
T 41000 47050 5 8 0 1 0 8 1
pinseq=18
T 41150 46900 9 8 1 1 0 0 1
pinlabel=PB4 (MISO)
T 41150 46900 5 8 0 1 0 2 1
pintype=io
}
P 41100 47100 40800 47100 1 0 1
{
T 41000 47150 5 8 1 1 0 6 1
pinnumber=17
T 41000 47250 5 8 0 1 0 8 1
pinseq=17
T 41150 47100 9 8 1 1 0 0 1
pinlabel=PB3 (MOSI/OC2)
T 41150 47100 5 8 0 1 0 2 1
pintype=io
}
P 41100 47300 40800 47300 1 0 1
{
T 41000 47350 5 8 1 1 0 6 1
pinnumber=16
T 41000 47450 5 8 0 1 0 8 1
pinseq=16
T 41150 47300 9 8 1 1 0 0 1
pinlabel=PB2 (SS/OC1B)
T 41150 47300 5 8 0 1 0 2 1
pintype=io
}
P 41100 47500 40800 47500 1 0 1
{
T 41000 47550 5 8 1 1 0 6 1
pinnumber=15
T 41000 47650 5 8 0 1 0 8 1
pinseq=15
T 41150 47500 9 8 1 1 0 0 1
pinlabel=PB1 (OC1A)
T 41150 47500 5 8 0 1 0 2 1
pintype=io
}
P 40800 47700 41100 47700 1 0 0
{
T 41000 47750 5 8 1 1 0 6 1
pinnumber=14
T 41000 47850 5 8 0 1 0 8 1
pinseq=14
T 41150 47700 9 8 1 1 0 0 1
pinlabel=PB0 (ICP1)
T 41150 47700 5 8 0 1 0 2 1
pintype=io
}
P 40800 49000 41100 49000 1 0 0
{
T 41000 49050 5 8 1 1 0 6 1
pinnumber=13
T 41000 49150 5 8 0 1 0 8 1
pinseq=13
T 41150 49000 9 8 1 1 0 0 1
pinlabel=PD7 (AIN1)
T 41150 49000 5 8 0 1 0 2 1
pintype=io
}
P 40800 49200 41100 49200 1 0 0
{
T 41000 49250 5 8 1 1 0 6 1
pinnumber=12
T 41000 49350 5 8 0 1 0 8 1
pinseq=12
T 41150 49200 9 8 1 1 0 0 1
pinlabel=PD6 (AIN0)
T 41150 49200 5 8 0 1 0 2 1
pintype=io
}
P 40800 49400 41100 49400 1 0 0
{
T 41000 49450 5 8 1 1 0 6 1
pinnumber=11
T 41000 49550 5 8 0 1 0 8 1
pinseq=11
T 41150 49400 9 8 1 1 0 0 1
pinlabel=PD5 (T1)
T 41150 49400 5 8 0 1 0 2 1
pintype=io
}
P 40800 46300 41100 46300 1 0 0
{
T 41000 46350 5 8 1 1 0 6 1
pinnumber=10
T 41000 46450 5 8 0 1 0 8 1
pinseq=10
T 41150 46300 9 8 1 1 0 0 1
pinlabel=PB7 (XTAL2/TOSC2)
T 41150 46300 5 8 0 1 0 2 1
pintype=io
}
P 40800 46500 41100 46500 1 0 0
{
T 41000 46550 5 8 1 1 0 6 1
pinnumber=9
T 41000 46650 5 8 0 1 0 8 1
pinseq=9
T 41150 46500 9 8 1 1 0 0 1
pinlabel=PB6 (XTAL1/OSC1)
T 41150 46500 5 8 0 1 0 2 1
pintype=io
}
P 40800 49600 41100 49600 1 0 0
{
T 41000 49650 5 8 1 1 0 6 1
pinnumber=6
T 41000 49750 5 8 0 1 0 8 1
pinseq=6
T 41150 49600 9 8 1 1 0 0 1
pinlabel=PD4 (XCK/T0)
T 41150 49600 5 8 0 1 0 2 1
pintype=io
}
P 40800 49800 41100 49800 1 0 0
{
T 41000 49850 5 8 1 1 0 6 1
pinnumber=5
T 41000 49950 5 8 0 1 0 8 1
pinseq=5
T 41150 49800 9 8 1 1 0 0 1
pinlabel=PD3 (INT1)
T 41150 49800 5 8 0 1 0 2 1
pintype=io
}
P 40800 50000 41100 50000 1 0 0
{
T 41000 50050 5 8 1 1 0 6 1
pinnumber=4
T 41000 50150 5 8 0 1 0 8 1
pinseq=4
T 41150 50000 9 8 1 1 0 0 1
pinlabel=PD2 (INT0)
T 41150 50000 5 8 0 1 0 2 1
pintype=io
}
P 40800 50200 41100 50200 1 0 0
{
T 41000 50250 5 8 1 1 0 6 1
pinnumber=3
T 41000 50350 5 8 0 1 0 8 1
pinseq=3
T 41150 50200 9 8 1 1 0 0 1
pinlabel=PD1 (TxD)
T 41150 50200 5 8 0 1 0 2 1
pintype=io
}
P 40800 50400 41100 50400 1 0 0
{
T 41000 50450 5 8 1 1 0 6 1
pinnumber=2
T 41000 50550 5 8 0 1 0 8 1
pinseq=2
T 41150 50400 9 8 1 1 0 0 1
pinlabel=PD0 (RxD)
T 41150 50400 5 8 0 1 0 2 1
pintype=io
}
P 43400 48200 43100 48200 1 0 0
{
T 43200 48250 5 8 1 1 0 0 1
pinnumber=1
T 43200 48350 5 8 0 1 0 2 1
pinseq=1
T 43050 48200 9 8 1 1 0 6 1
pinlabel=(RESET) PC6
T 43050 48200 5 8 0 1 0 8 1
pintype=io
}
]
{
T 40900 50900 5 10 0 0 0 0 1
footprint=DIP28N
T 43100 50700 5 10 1 1 0 6 1
refdes=U6
T 40900 51700 5 10 0 0 0 0 1
device=ATmega8
}
C 44100 48000 1 0 0 EMBEDDEDnmos-3.sym
[
T 44800 48600 8 10 0 1 0 0 1
refdes=Q1
T 44700 48500 5 10 0 0 0 0 1
description=generic N channel MOS transistor (enhancement type)
T 44700 48500 5 10 0 0 0 0 1
numslots=0
T 44700 48500 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
L 44500 48400 44500 48200 3 0 0 0 -1 -1
L 44350 48400 44500 48400 3 0 0 0 -1 -1
L 44300 48600 44300 48200 3 0 0 0 -1 -1
L 44350 48275 44350 48125 3 0 0 0 -1 -1
L 44350 48475 44350 48325 3 0 0 0 -1 -1
L 44350 48675 44350 48525 3 0 0 0 -1 -1
P 44600 48200 44600 48000 1 0 1
{
T 44400 48000 5 10 0 1 0 0 1
pinnumber=S
T 44400 48000 9 10 0 1 0 0 1
pinlabel=S
T 44400 48000 5 10 0 0 0 0 1
pinseq=3
T 44400 48000 5 10 0 0 0 0 1
pintype=pas
}
P 44600 48600 44600 48800 1 0 1
{
T 44400 48700 5 10 0 1 0 0 1
pinnumber=D
T 44400 48700 9 10 0 1 0 0 1
pinlabel=D
T 44400 48700 5 10 0 0 0 0 1
pinseq=1
T 44400 48700 5 10 0 0 0 0 1
pintype=pas
}
P 44100 48200 44300 48200 1 0 0
{
T 44100 48300 5 10 0 1 0 0 1
pinnumber=G
T 44100 48300 9 10 0 1 0 0 1
pinlabel=G
T 44100 48300 5 10 0 0 0 0 1
pinseq=2
T 44100 48300 5 10 0 0 0 0 1
pintype=pas
}
L 44350 48400 44450 48350 3 0 0 0 -1 -1
L 44350 48400 44450 48450 3 0 0 0 -1 -1
L 44350 48200 44600 48200 3 0 0 0 -1 -1
L 44350 48600 44600 48600 3 0 0 0 -1 -1
]
{
T 44700 48500 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
T 44800 48600 5 10 1 1 0 0 1
refdes=Q2
}
C 44100 49300 1 0 0 EMBEDDEDnmos-3.sym
[
T 44800 49900 8 10 0 1 0 0 1
refdes=Q3
T 44700 49800 5 10 0 0 0 0 1
description=generic N channel MOS transistor (enhancement type)
T 44700 49800 5 10 0 0 0 0 1
numslots=0
T 44700 49800 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
L 44500 49700 44500 49500 3 0 0 0 -1 -1
L 44350 49700 44500 49700 3 0 0 0 -1 -1
L 44300 49900 44300 49500 3 0 0 0 -1 -1
L 44350 49575 44350 49425 3 0 0 0 -1 -1
L 44350 49775 44350 49625 3 0 0 0 -1 -1
L 44350 49975 44350 49825 3 0 0 0 -1 -1
P 44600 49500 44600 49300 1 0 1
{
T 44400 49300 5 10 0 1 0 0 1
pinnumber=S
T 44400 49300 9 10 0 1 0 0 1
pinlabel=S
T 44400 49300 5 10 0 0 0 0 1
pinseq=3
T 44400 49300 5 10 0 0 0 0 1
pintype=pas
}
P 44600 49900 44600 50100 1 0 1
{
T 44400 50000 5 10 0 1 0 0 1
pinnumber=D
T 44400 50000 9 10 0 1 0 0 1
pinlabel=D
T 44400 50000 5 10 0 0 0 0 1
pinseq=1
T 44400 50000 5 10 0 0 0 0 1
pintype=pas
}
P 44100 49500 44300 49500 1 0 0
{
T 44100 49600 5 10 0 1 0 0 1
pinnumber=G
T 44100 49600 9 10 0 1 0 0 1
pinlabel=G
T 44100 49600 5 10 0 0 0 0 1
pinseq=2
T 44100 49600 5 10 0 0 0 0 1
pintype=pas
}
L 44350 49700 44450 49650 3 0 0 0 -1 -1
L 44350 49700 44450 49750 3 0 0 0 -1 -1
L 44350 49500 44600 49500 3 0 0 0 -1 -1
L 44350 49900 44600 49900 3 0 0 0 -1 -1
]
{
T 44700 49800 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
T 44800 49900 5 10 1 1 0 0 1
refdes=Q4
}
C 44100 50600 1 0 0 EMBEDDEDnmos-3.sym
[
T 44800 51200 8 10 0 1 0 0 1
refdes=Q5
T 44700 51100 5 10 0 0 0 0 1
description=generic N channel MOS transistor (enhancement type)
T 44700 51100 5 10 0 0 0 0 1
numslots=0
T 44700 51100 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
L 44500 51000 44500 50800 3 0 0 0 -1 -1
L 44350 51000 44500 51000 3 0 0 0 -1 -1
L 44300 51200 44300 50800 3 0 0 0 -1 -1
L 44350 50875 44350 50725 3 0 0 0 -1 -1
L 44350 51075 44350 50925 3 0 0 0 -1 -1
L 44350 51275 44350 51125 3 0 0 0 -1 -1
P 44600 50800 44600 50600 1 0 1
{
T 44400 50600 5 10 0 1 0 0 1
pinnumber=S
T 44400 50600 9 10 0 1 0 0 1
pinlabel=S
T 44400 50600 5 10 0 0 0 0 1
pinseq=3
T 44400 50600 5 10 0 0 0 0 1
pintype=pas
}
P 44600 51200 44600 51400 1 0 1
{
T 44400 51300 5 10 0 1 0 0 1
pinnumber=D
T 44400 51300 9 10 0 1 0 0 1
pinlabel=D
T 44400 51300 5 10 0 0 0 0 1
pinseq=1
T 44400 51300 5 10 0 0 0 0 1
pintype=pas
}
P 44100 50800 44300 50800 1 0 0
{
T 44100 50900 5 10 0 1 0 0 1
pinnumber=G
T 44100 50900 9 10 0 1 0 0 1
pinlabel=G
T 44100 50900 5 10 0 0 0 0 1
pinseq=2
T 44100 50900 5 10 0 0 0 0 1
pintype=pas
}
L 44350 51000 44450 50950 3 0 0 0 -1 -1
L 44350 51000 44450 51050 3 0 0 0 -1 -1
L 44350 50800 44600 50800 3 0 0 0 -1 -1
L 44350 51200 44600 51200 3 0 0 0 -1 -1
]
{
T 44700 51100 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
T 44800 51200 5 10 1 1 0 0 1
refdes=Q6
}
N 43400 48200 44100 48200 4
N 43400 48400 44100 48400 4
N 44100 48400 44100 49500 4


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