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Re: [f-cpu] F-CPU architecture...
And the interface to the DMA engine is not yet defined.
I wish something like on the SHARC is available
(DMA block descriptors are a linked list stored in RAM)
but this requires further thinking.
It doesn't have to be a list.
In the SHARC, it is. and it is pretty practical, you can make the list
cyclic if you want, for example.
it's really a great piece of engineering. read the docs :-)
An array will work fine, too, and requires less hardware -
incrementing a pointer is easier than loading a new one from memory.
The way i see the DMA engine is :
- used by application SW to move large blocks from one address to another
That's not a DMA, that's a "blitter". The difference is that DMAs don't
move data from memory to memory.
- configurable at will
- sends an IRQ or sets a flag when one block is finished
And/or (configurable) when all blocks are finished.
- has a queue of tasks (or a linked list, or whatever)
You speak about an array, but how and where ?
In main memory. That's the only place where arbitrary space is
available. Where does SHARC store its descriptor list?
A ring buffer would also be possible with minimal overhead.
same as above : located where, and what kind of access ?
a local DMA engine should be accessible from outside, and vice versa
(a remote DMA should be able to be triggered)
What do you mean when you say "remote DMA"?
We're not talking about RDMA now, are we? That's a matter of two DMA
engines (one local, one remote) communicating via a high-speed bus.
And it has the advantage that you can easily add new requests while
DMA is still running.
with a linked list too, there are suitable flags.
You may get race conditions if the queue is updated in the very moment
the DMA engine reads the last descriptor. Unless, of course, you build a
linked list at startup and only modify descriptor data later. But that's
just another kind of ring buffer.
All we need is four parameters: address and size of the DMA descriptor
table, and "head" and "tail" offsets into the table. The "head" will
be maintained by the DMA engine, and when head and tail are the same
(simple XOR), DMA stops until the OS moves the tail to a new position
(after writing new descriptors, of course).
Other parameters are needed :
- priority (multiple DMAs should be able to take place out of order and
- trtigger IRQ or not
That should be configurable per-block, in the descriptors.
and a few others i forget.
Look at the SHARC and the Cell "SPU"s which also have DMA engines.
Michael "Tired" Riepe <michael@xxxxxxxx>
X-Tired: Each morning I get up I die a little
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