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Re: [f-cpu] F-CPU architecture...


Yann Guidon wrote:

after 5 minutes, i came to this conclusion :
SMT or threadlets can certainly be done in FC1, but not in FC0.

your idea is quite smart, but beside support from compilers, a more pragmatic
issue arises : it goes against one of the core ideas in FC0.

Well, I didn't intend to implement it in FC0. Although we could include fake fork/join instructions for compatibility. It's just a few gates in the instruction decoder. As I said, fork would resemble jump, and join would be a no-op.

It could also be interpreted the other way round: fork would "schedule" a jump, and join would execute it. But that's too complicated to implement.

Now, adding support for multiple instruction streams (whether they share or not the register set)
adds a minimum of one stage : the instruction must be selected among the threads,
and this decision is ideally based on resource availability (is the register's value available
somewhere on the Xbar or is the LSU ready ?).

We have to check that anyway because the core must stall when required resources (EUs, buses, data) are not available. With SMT or threadlets, we can perform those checks in parallel, and select the next instruction from a thread(let) that is executable at that particular cycle. Or stall if none of them is able to continue.

But you're right, the result would probably arrive too late in FC0.

I propose that we finish FC0 the way we designed it almost 5 years ago,
and then we can move to more sophisticated stuffs :-)

And I do not object. :-)

Let's just keep the idea in mind for later. And in case somebody else wants to patent it, I'll claim prior art. :-)

Michael "Tired" Riepe <michael@xxxxxxxx>
X-Tired: Each morning I get up I die a little
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