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Re: CAS and spinlocks (was: Re: [f-cpu] another DATE report)

----- Original Message -----
From: Michael Riepe <michael@stud.uni-hannover.de>
To: <f-cpu@seul.org>
Sent: Tuesday, March 19, 2002 12:04 PM
Subject: Re: CAS and spinlocks (was: Re: [f-cpu] another DATE report)

> On Tue, Mar 19, 2002 at 03:56:47AM +0100, Christophe wrote:
> > Well there is a lot of missing things in VHDL source so it would be quite
> > difficult for me to do something since I don't have the slight idea of
> > implementation you want to make, especially regarding with memory. And
> > don't forget, I'm a programmer, not a VHDL guru. I can read VHDL but don't
> > think for you. If you want me to do something I first need more materials
> > I can find in your source to be able to figure out how to proceed (a lot of
> > details about the implementation of your F-CPU sound fuzzy to my ears for
> > moment).
> Please go ahead... which details?

There is no LSU source for example. What are its signals, its internals ? how
are the register set and other functional units connected ? etc.

> [...]
> > Anyway, I'm not speaking about to have an instruction CAS2 but something
> > two CAS linked IF IT IS POSSIBLE.
> Since two CAS don't make a CAS2, that wouldn't make much sense.

I mean something a normal CAS and a linked CAS like we can find for ll/sc and
llp/scp :

ll        [r1],r3 ; load linked
llp      [r2],r4 ; load linked pipelined
scp   r6,[r2] ; r6 written into [r2] only if last memory slots of ll and llp
not modified
jnz    0b
sc     r5,[r1] ; r5 written into [r1] only if last memory slot of ll not
jnz    0b

But forget.

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