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Re: CAS and spinlocks (was: Re: [f-cpu] another DATE report)


Christophe wrote:
> From: Michael Riepe
> > On Tue, Mar 19, 2002 at 03:56:47AM +0100, Christophe wrote:
> > > Well there is a lot of missing things in VHDL source so it would be quite
> > > difficult for me to do something since I don't have the slight idea of
> > > implementation you want to make, especially regarding with memory. And please
> > > don't forget, I'm a programmer, not a VHDL guru. I can read VHDL but don't
> > > think for you. If you want me to do something I first need more materials than
> > > I can find in your source to be able to figure out how to proceed (a lot of
> > > details about the implementation of your F-CPU sound fuzzy to my ears for the
> > > moment).
> >
> > Please go ahead... which details?
> There is no LSU source for example. What are its signals, its internals ? how
> are the register set and other functional units connected ? etc.

concerning the LSU, there is a strong disagreement between nicO and me...
i have a personal opinion and method, while nicO's point of view is more
academic. Currently, i try to finish the R7, integrate new VHDL tools
(make the ncsim simulator work, not only the compiler, plus add Riviera
support), add some old simple EU (INC, POPC), make another version of SHL...
and make a major update to the YGASM, update the websites, not
counting all the non-F-CPU duties of everyday...

starting to code from the LSU side is not very wise (i tried and failed).
the plan is more : do all EU, add the R7 and Xbar, then the scheduler
and the instruction decoder. These parts make the "execution pipeline"
which can be more or less taken apart. Then add the TLB, LSU and fetcher
(three units which are very closely tied). The L1 cache comes on top
of it, as well as the other memory interfaces and I/O.

I insist on plugging the local SDRAM controller directly to the LSU/fetcher,
as well as the L2 and the I/O bus (so the LSU has 4 ports from the external
side and 1 port from the pipeline side). nicO wants all cache levels
to be "unfolded" or "chained" (L1 plugged to L2 which is plugged to SDRAM...)
but the management is very different and creates some coherency problems
and increases the latency.

just make your choice.

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