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Re: CAS and spinlocks (was: Re: [f-cpu] another DATE report)

On Tue, Mar 19, 2002 at 10:21:38PM +0100, Christophe wrote:
> > Please go ahead... which details?
> There is no LSU source for example. What are its signals, its internals ? how
> are the register set and other functional units connected ? etc.

That's something we still have to work on.  I have to admit that I
don't have an exact picture either, so we will have to talk about it,
preferably on this mailing list.

The LSU will probably have

	- an interface to the Xbar, similar to the execution units:
		- a 64-bit address input port
		- a 64-bit data input port (write port)
		- a 64-bit data output port (read port)
		- mode control lines coming directly from the opcode
			(load/store, operand size, endian, stream hints, flush)
		- an `enable' line indicating that the inputs are valid
	- an interface to the data cache
		(this is not yet clear at all)
	- a number of additional control lines
		(not clear either)

Feel free to add more details...

 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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