Re: gEDA-user: terminators

[DJ Delorie <dj@xxxxxxxxxxx>]

> With the dimensions you just quotes, an sdram write will gain some setup 
> time because the clock gets there later and looses some hold time for 
> the same reason.  1.7" * 170ps/inch = 289 pS.  Peeking at the data 
> sheet, that sdram has some tight specs - like 0.8 nS setup.  So that 
> mismatch in line length is going to cost you a little less than 1/2 of 
> your budget.

If the traces are short enough and delays short enough, I can do the
setup a half cycle earlier.  It makes the state machine a little more
difficult, though.  It means my "time window" is now 3.75 nS instead
of 7.5 nS but it lets me separate data changes and data sampling.

I think the 3A allows me to generate an internal clock that's a
quarter phase off from the external clock, too.  That gives me another
2nS of setup and hold times.

> Do you have the other side of your board to route on?  Maybe that would 
> help.

I do, but I have to manually solder in every single via.  My vias are
small, but not *that* small.  Plus, I can't put vias under anything.

> Why don't you use the PQFP208 fpga and use the extra pins for debugging? 

The 3A is not available in that package.  The 3E requires 2.5v during
programming.  Kinda limits my options :-(

> Hey, just wondered if you turn the SDRAM 90 degrees, does that help even 
> out the traces?

I don't know.  I'll have to try and see.  There's still the 0.8 inches
of the sdram's length.  I think my best bet is to keep the sdram
oriented the way it is, but run the traces to the right-side pins
between the left-side pins and under the chip.  That way, I only have
to make up 450mil of difference due to the chip, and 250 mil due to
the FPGA pinout.  That's only 700 mil, if I put the chips that far
apart a serpentine can make it up.


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