Re: gEDA-user: terminators

[gene glick <carzrgr8@xxxxxxxxxxxxx>]

DJ Delorie wrote:
>> Hey Steven, that's a pretty interesting analysis.  I just want to add 
>> something from Dr. Howard Johnson's book on this stuff.  His claim is 
>> that you can treat a pcb trace as a lumped system if the trace is less 
>> than 1/4 * 'length of the edge'.  Well, at 170 ps/inch the length of the 
>> edge is about 5.8" - that's exactly 1/2 your result.
> 
> If I remove the LA connector and shove the sdram closer to the fpga, I
> get a trace length range of 2027 mils (CLK) down to 281 mils (DQ7), a
> mis-match of 1.7 inches, or just under 1/3 of 5.8".
> 
> I wonder if I could drive the shorter traces less than the longer
> ones, to match up the edges at the sdram?
> 
> 
sounds tricky to do in practice.

With the dimensions you just quotes, an sdram write will gain some setup 
time because the clock gets there later and looses some hold time for 
the same reason.  1.7" * 170ps/inch = 289 pS.  Peeking at the data 
sheet, that sdram has some tight specs - like 0.8 nS setup.  So that 
mismatch in line length is going to cost you a little less than 1/2 of 
your budget.

I think you are going to need nice crisp edges in order to make the 
timing specs.  Keeping the data and clock lines relatively equal will 
eliminate skew headaches.

Do you have the other side of your board to route on?  Maybe that would 
help.

Why don't you use the PQFP208 fpga and use the extra pins for debugging? 
  That will get rid of the stub junk to the emulator.  Then move the the 
SDRAM around to even up the trace length.  Terminate the clock line 
(series terminate at fpga, RC at the other end).

Hey, just wondered if you turn the SDRAM 90 degrees, does that help even 
out the traces?




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