Re: gEDA-user: terminators

[gene glick <carzrgr8@xxxxxxxxxxxxx>]

> 
> So, long story short... I need to redesign the board :-(

that's funny :)

Seriously though, as long as the signal is clean and you make the 
setup/hold times then you are golden.  I don't think %skew is the best 
way to analyze it.  Use the absolute time, draw yourself a timing 
diagram and see if you are close.

You *could* always jockey the output timing from your fpga - but that's 
not a great way to fix it.  Didn't someone else mention using a pll? 
That could work too. But, honestly, from what I see on your board what's 
the problem besides the stubs?

Oh, and make sure to set the constraints on your fpga so the timing is 
right-on.



_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user