Re: gEDA-user: terminators

[Darrell Harmon <dlharmon@xxxxxxxxxxxx>]

On Mon, Apr 6, 2009 at 9:35 PM, DJ Delorie <dj@xxxxxxxxxxx> wrote:
>
> If I remove the LA connector and shove the sdram closer to the fpga, I
> get a trace length range of 2027 mils (CLK) down to 281 mils (DQ7), a
> mis-match of 1.7 inches, or just under 1/3 of 5.8".
>
> I wonder if I could drive the shorter traces less than the longer
> ones, to match up the edges at the sdram?
>

I would get rid of the LA connector. On all my SDRAM designs, I
concentrated on short trace lengths rather than matching. Most of my
traces were less than 1 inch. All seem to work well at 133 MHz. You
may be able to delay some signals in the FPGA with DCMs or IOB delays.

I have had one failed board with high speed signals. The nets were all
well matched in length (+- 1 inch), but over 6 inches long and with 2
connectors. It was an FPGA board I made connected to an adaptor board
connected to a Xilinx FPGA development kit. The traces on the XIlinx
board are 4 inches. I was attempting to use 3.3V CMOS, and was having
severe problems with reflections. I gave that approach up and will be
building my own board with the FG676 Xilinx FPGA on it so that I can
reduce trace lengths and/or use LVDS. I was forced into a high data
rate by only having 18 pins in each direction and needing to move 250
MB/s in each direction.

Darrell Harmon


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