Re: gEDA-user: terminators

[Tim Hanson <sideskate@xxxxxxxxx>]

DJ -
Before you create another board, could you try using a razor to cut
all the logic analyzer traces right near or at the vias?  This may
help, and if the board doesn't work now, there is no harm in a minute
with the knife.
I've laid out an interface to a 133Mhz SDRAM, and the path lengths
were similar to yours.  Works great.  No LA connector, though.
Tim

On Mon, Apr 6, 2009 at 10:35 PM, DJ Delorie <dj@xxxxxxxxxxx> wrote:
>
>> Hey Steven, that's a pretty interesting analysis.  I just want to add
>> something from Dr. Howard Johnson's book on this stuff.  His claim is
>> that you can treat a pcb trace as a lumped system if the trace is less
>> than 1/4 * 'length of the edge'.  Well, at 170 ps/inch the length of the
>> edge is about 5.8" - that's exactly 1/2 your result.
>
> If I remove the LA connector and shove the sdram closer to the fpga, I
> get a trace length range of 2027 mils (CLK) down to 281 mils (DQ7), a
> mis-match of 1.7 inches, or just under 1/3 of 5.8".
>
> I wonder if I could drive the shorter traces less than the longer
> ones, to match up the edges at the sdram?
>
>
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