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Re: gEDA-user: PCB gcode generation



On Sun, 2011-05-01 at 00:11 +0200, Alberto Maccioni wrote:

> I hope these comments won't be interpreted again as "don't change my code".
> By the way, it seems that my original gcode patch is formally still
> uncommitted; since it has already made it to a release (ok, a real
> developer cleaned everything up) why not change its status? Or is it
> dependent on the documentation?

Thanks for the explanation. I was actually helping someone on #geda IRC
earlier who was using the gcode HID to produce a toolpath to cut out a
panel of boards, so I got a chance to dig into it a little, even firing
up EMC2 in simulation mode to view the toolpaths it produced.

I'm uncertain what you mean by you "original gcode patch is formally
still uncommitted". Do you mean that the bug is open, or that not all of
your work has been committed?

If it is just a matter of closing the bug, please feel free to mark the
bug "Fix released", it is probably just an oversight on our part. We're
all keen for interested parties to contribute and take action on those
areas of the project which interest them.



In case you're interested about the stuff I was talking about on #geda:

As a feature request which came from that discussion, it seems that it
might be nice to provide the option of special casing the handling of
"outline" layers.

The expected convention is to put a narrow series of lines around the
boards to denote their outline, the path of these lines forms the the
centre-line of the finished board. The problem we were addressing is
that the gcode export (not unreasonably) treated this as a track to be
isolation routed.

As a quick workaround, I patched a new action on top of the PCB+GL
code-base. The PCB+GL branch contains a simple algorithm to calculate a
polygon (or polygons for a panel of boards) representing the physical
board shape. PCB+GL uses this to render the solder-mask layer
accordingly in its 3D (and 2D) rendering.

The simple action I wrote uses the existing "outline" layer to determine
the board shape, then rips out the contents of the original "outline"
and replaces it with polygons. (One polygon per board). The gcode
exporter then produced output suitable for cutting the boards out (using
EMC2 to handle the tool offset etc..).


Best wishes,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)

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