Re: gEDA-user: Subnets

[John Griessen <john@xxxxxxxxxxxxxx>]

Rick Collins wrote:
> First, I want to say that power supply bypassing is probably not a good 
> example to use since there are a number of ways to layout such things 
> and many people will disagree about the "optimal" way of doing it.

I think it's an OK example.  There's no need to assume any way of doing bypass
caps other than "short distance".  I'm not saying a hard coded
make-bypass-cap-connection would ever get into gschem or pcb, it's just
that top down schematic driven design has lots of value and plenty of fans.
The example is fine if you don't worry about it being more than a first cut
at why you want subnets in a net.

 I would suggest that it would make sense to
> figure out just what autorouters can do in terms of specialized routing 
> of portions of a net, then see what info the autorouter needs to be told 
> of specialized routing.

After seeing some of Tony's topologic router output, and my time doing chip layout
and exposure to high dollar tools, my gut says, we're onto something.
Why do it only after proven ways exist?  That's too late for planning purposes.


> I have seen nets that need to be routed with some ordering of the pins.  
> e.g. in ECL the driver is at one end of the net, the terminator at the 
> other and the receiver is in between, near the terminator.  There are 
> similar issues with routing LVDS and high speed signals.  Can this be 
> conveyed using subnets?  

Yes, that is a good example of subnets being valuable. Flags for it?
Kinda complicated, but there's going to be a way.

John Griessen
--
Ecosensory   Austin TX


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