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Re: gEDA-user: wishful UI



At 11:44 AM 8/16/2010, Stefan Salewski wrote:
On Mon, 2010-08-16 at 15:51 +0200, Armin Faltl wrote:

> >
> Just to make it known, "a subnet is a point to point connection within a
> net" was the
> one and only DEFINITION of what a sub net is I found and understood. All
> other ways
> I can conceive are generalizations of that, ie. "a subnet is a list of 2
> or more pins within
> a net".

I think we should try to find a better name for the connection between
two nodes in a net, maybe segment?

In the layout program I use, a segment is a single section of a PWB route between two points. That is, it is the shortest specified portion of a route. The entire connected entity is a net and a connection between two pins or a T vertex is a trace. The trace is equivalent to what you are trying to describe.

A lot of the discussion in this list is conducted as if the functioning of schematics were the only consideration. Why not start with what you are trying to do in the layout, consider what the layout tool needs to make that happen, then trace that back to what is needed in the schematic to support the layout? So much of this conversation just seems so disconnected from what might be needed to do real work.

If you want to consider impedance, then lets start with the ways you would want to control impedance and figure out just what that demands of layout and then the schematic? Normally when I am controlling impedance, I am using point to point connections with no branches or stubs. But if they are kept short, a stub can be used with impedance controlled nets. Likewise, I seldom have more than one receiver on an impedance controlled nets, but I can see where a bus might need to be impedance controlled even with many drivers and receivers. So it seems like in layout you would need impedance on an entire net, not just a trace or subnet. When would you want a layout to control impedance on a portion of a net and not the entire net?

Rick


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