Re: gEDA-user: New user - Hierarchy problem

["Steven Taylor" <steven.taylor56@xxxxxxxxxxxxx>]

I had put the "source=" attribute in the symbol for the underlying  
schematic page. That was enough for the proper hierarchy operations except  
for the drc and netlist generation. As per John's sample schematics, I  
added a "source=" attribute on each of the instantiated symbols at the top  
level and now everything is fine. Evidently the "source=" attribute  
doesn't get promoted, if that is the right context and terminology, and  
the drc and netlist operations need it to be at the top level. There  
probably is a way to ensure that the attribute is promoted, that I'll have  
to leave to another day. It is now working well enough for me to complete  
this project.

Thanks to all who helped,
Steve

On Mon, 11 Feb 2008 14:55:51 -0800, John Griessen <john@xxxxxxxxxxxxxx>  
wrote:

> Steven Taylor wrote:
>> My symbol, that I created, that represents my lower level schematic has
>> pins with only pin numbers, pinseq numbers, and pin labels. The pin  
>> labels
>> match the refdes on the IO connectors on the underlying schematic.
>
> OK, How about the refdes of the symbol that corresponds to the leaf cell  
> schematic
> placed in the to schematic?
> Did you give those different names?  Mine have names like S1, S2, S3,  
> etc.
>
> Want me to create a schematic set with embedded symbols and send it to  
> you for another example to follow?
> The schematic is for some free-published hardware... no problem to look  
> at it.
>
> John Griessen
>



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