Re: gEDA-user: Google SoC : Potential Candidate seeking Info

[al davis <ad151@xxxxxxxxxxxxxxxx>]

Welcome ...  they are all good ones, but I like the one Steve 
suggested the best.


On Wednesday 11 February 2009, Aanjhan R wrote:
> 1. Usability improvements for ngspice/Gnucap - Under gaf

There is certainly lots of room for improvement, but I must warn 
you that there have been lots of failed attempts at this in the 
past.

To be successful, you need to not think of it as a GUI project.  
The biggest problem is seamlessly moving the data around, in 
all directions.  (I mean all, not "both".)  If you want to 
tackle the data movement, with a new translator system, that 
would help a lot, and build the base that is needed for the GUI 
and other things.

> 2. More "interesting" integrations with other tools. The new
> Tcl interface adds a bunch of possibilities. I know one guy
> is using it to allow remote control from emacs through a
> bridge server. (Under GTKWAVE - I would like to know if htere
> are specific "interesting" integrations as I am not getting
> the whole picture behind this project proposal)

That points to seamlessly moving the data around again.  This 
keeps coming up.

> 3. Porting of missing analysis, (noise, pz, disto, hb, etc.)
> from other free simulators (under gnucap)

All good projects ..  There is someone now working on noise and 
hb.  pz and disto would be good summer projects.  "pz" is 
fairly easy, if it is based on AC analysis, because the whole 
model interface is already working.   "disto" is harder because 
of the model interface.  You will learn a lot.

> 4. Add uwire (unresolved net) support  - Under Icarus

Steve can comment on this one.

On Wednesday 11 February 2009, Stephen Williams wrote:
>> Given the apparent bent towards analog in your selection of
>> candidate projects, might I suggest you take a look at the
>> "gnucap Code Generator" on the Icarus Verilog projects page?
>> This is something that Al has been wanting, and also puts to
>> use some of the nascent analog support in Icarus Verilog
>> proper.

I like this one too.  It is an enabler that will make other 
enhancements easier, and something that is desperately needed 
as a model compiler.  There are lots of people who want it and 
some real experts who can help.






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