Re: gEDA-user: how to make DRC ignore "outline" layer?

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Wed, 2010-02-10 at 21:33 -0600, Mark Rages wrote:
> On Wed, Feb 10, 2010 at 8:55 PM, DJ Delorie <dj@xxxxxxxxxxx> wrote:
> >
> >> Bonus points for a patch which wraps the magic test in a new macro /
> >> function, something like:
> >>
> >>  if (!LAYER_IS_COPPER (Layer))
> >>     continue;
> >>
> >> To skip the connectivity tests for other non-copper layers.
> >
> > This is the layer mega-patch I've been (sadly) talking about for years
> > now.
> >
> > The parser supports an extra string in the Layer() syntax for type and
> > flags, but we do nothing with it yet.
> >
> 
> What about making the outline lines / arcs cut polys on the copper
> layers?  Any downsides to that?

Do you want it to do that?

My money would be on having it based on a flag.

However, I do know that (for example), on Altium, the outline defined by
the board will create a boarder on any power plane layers, such that
they stay a given clearance away from the board edge.

There is no real defined rule for what the "outline" means. I think,
most commonly you might its center-line used as the board edge. I tend
to make it very small (10mil), so I'm not affected by what the fab-house
decide to do with it.

If you wanted to have it cutting copper on other layers, you would need
a better knowledge of what constitutes the outline. Also, I'm not 100%
convinced you will want to define your outline width to match the
clearance desired on other layers, even if you know the board house will
take the center-line. It might look cluttered on screen. I could be
wrong there though.




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