Re: gEDA-user: Difficulty in border areas

[Karel Kulhavy <clock@xxxxxxxxxxxxx>]

> This is the way we work with large board designs at work, typically for
> decoupling caps and PLL filters for example we bring in a bunch of
> components and group them outside the board outline so that components
> that belongs to the same filter for ere next to each other. Then we
> can figure out how to arrange the filter components for example
> without having to worry about getting DRC errors or decide where
> exactly the filter should go.

a) What is a typical PLL filter composed from?
b) What is it's purpose in the PLL circuit? Is it a lowpass to filter
out the phase error signal?
c) What is a typical PLL solution if I want to say make 100MHz from 33.3MHz?
d) What if I want to make 44.1kHz from say 33MHz and need it
super-hyper-roxx0r stable because am using it for feeding Hi-Fi audio DAC and
even the tiniest jitter would be audible?  How do I do it with PLL?

Cl<