Re: gEDA-user: Difficulty in border areas

[Daniel Nilsson <daniel@xxxxxxxxxxxxxxx>]

On Thu, Jan 06, 2005 at 11:58:08PM +0000, Karel Kulhavy wrote:
> > This is the way we work with large board designs at work, typically for
> > decoupling caps and PLL filters for example we bring in a bunch of
> > components and group them outside the board outline so that components
> > that belongs to the same filter for ere next to each other. Then we
> > can figure out how to arrange the filter components for example
> > without having to worry about getting DRC errors or decide where
> > exactly the filter should go.
> 
> a) What is a typical PLL filter composed from?

I should probably have been a little clearer, I meant to say filter
for the analog power supply of PLL based clock drivers. These power
filter are used to filter out lowe frequency noise present on the
power planes and are typically a combination of capacitors and
inductors or resistor.

> b) What is it's purpose in the PLL circuit? Is it a lowpass to filter
> out the phase error signal?

To filter out noise on the power plane typically in the 100kHz to 1Mhz
range coming from switch mode power supplies.

> c) What is a typical PLL solution if I want to say make 100MHz from
> 33.3MHz?

Try to find a clock driver with a programmable divider and set the
feedback to divide by 3 or if that is not possible you can have the
feedback path divide by 6 thus creating a 200MHz oscillator frequency
and then divide the output by 2.

> d) What if I want to make 44.1kHz from say 33MHz and need it
> super-hyper-roxx0r stable because am using it for feeding Hi-Fi audio DAC and
> even the tiniest jitter would be audible?  How do I do it with PLL?

Sorry, don't know much about audio design... I do know that all PLL
circuits will have jitter though, there is no such think as a zero
jitter PLL that I've ever heard of.

-- 
Daniel Nilsson