Re: gEDA-user: Spice netlister

[Paul Tan <pt75234@xxxxxxx>]

Hi All,

On Sun, 20 Jan 2008 10:19 am, John Doty wrote:

>It would be nice to be able to suppress the automatic netlist
>flattening that gnetlist does, giving the back end the option of
>creating a hierarchical netlist in the source= case.

There is an option in system-gnetlistrc to disable flat hierarchy:

(hierarchy-traversal  "disable")

This is how the gnet_hier_verilog.sh in gEDA utiliity use it to
traverse the hierarchy. if you have install gEDA utility pacakge,
gnet_hier_verilog.sh should normally be in /usr/bin/.

Best Regards,
Paul Tan



-----Original Message-----
From: John Doty <jpd@xxxxxxxxxxxxx>
To: gEDA user mailing list <geda-user@xxxxxxxxxxxxxx>
Sent: Sun, 20 Jan 2008 10:19 am
Subject: Re: gEDA-user: Spice netlister



On Jan 20, 2008, at 6:51 AM, a r wrote:

> I have looked closer into the sources and into the "RF_Amp" example
> circuit.
>
> If a "spice-subcircuit-LL" component is added to the schematic the
> netlister will wrap it up with a .subckt/.ends cards. That's pretty
> close to the behaviour I wanted. There are some issues, though:
> 1. It forces me to add a simulation card to the schematic. In general
> cases that something I'd like to avoid (it is OK for testbench
> schematics, though).

I don't see why that's a big deal.

> 2. All nested models or ".include" cards (if "-I" option was used) are
> added inside the .subckt. That may cause problems with spice
> simulators that do not like such nested constructs.

Indeed, that's an annoyance, not only for simulation but for layout.
The layout contractor I work with wants to see each cell in the
netlist exactly once, at top level, not nested. But a little
postprocessing gets the job done here.

> 3. There are special "spice-subcircuit-IO" components used for making
> subcircuit pins. Does it mean the netlister cannot cope with "normal"
> instance pins?

There are a couple of different ways to do hierarchy. If you use
source= to associate the symbol to its subcircuit, you use the
symbols in the "io" library to make your connections in the
subcircuit schematic. In this case, the netlister expands all
hierarchy automatically, making a flat netlist.

On the other hand, if you use the model-name= attribute to make the
association, you need to use the spice-subcircuit-IO symbols in the
subcircuit schematic. In this case, you won't get a flat netlist, but
if you also use the file= attribute you'll get a nested hierarchical
netlist, which I don't find terribly useful.

One of the difficulties is that SPICE pin associations are by pin
order (pinseq=), not by name. If you're importing a macromodel or
cell from outside the gEDA world, you won't even have a subcircuit
schematic.

It would be nice to be able to suppress the automatic netlist
flattening that gnetlist does, giving the back end the option of
creating a hierarchical netlist in the source= case.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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