Re: gEDA-user: Spice netlister

["a r" <nbs.public@xxxxxxxxx>]

On Jan 21, 2008 6:02 PM, John Doty <jpd@xxxxxxxxxxxxx> wrote:
>
> On Jan 21, 2008, at 10:43 AM, John Griessen wrote:
>
> > John Doty wrote:
> >
> >>> - clean schematics are needed for LVS,
> >>
> >> What's LVS? Please don't assume we know your jargon.
> >>
> > Layout Versus Schematic checker.  EDA jargon.  Chip design jargon.
> > Our jargon.
> >
>
> The people I work with call it "postlayout verification", and the
> schematic isn't directly involved: we do it at the netlist level. I
> don't see how you'd do it at the schematic level: the extracted
> netlists from the layout correspond to schematics that are humanly
> incomprehensible! But again, I am very far from the VLSI "mainstream".

That's a bit off-topic but it's better if I explain this topic a bit.

LVS is a method of comparing layout vs. schematics. It starts with two
netlists - one obtained from schematics (usually a spice-like .cdl
format, verilog gate-level netlists for logic), the other extracted
from layout (without parasitics). In fact, you can compare netlists
obtained from two schematics (sometimes it's called SVS) or two layout
(this is rarely used - layouts are usually compared geometrically).
It's basically a tool, which says that the layout you have drawn is
same as schematics you have started from (in terms of primitive
devices used and their interconnections).

LVS is one of _layout_ verification methods. Others are DRC (often
separated into several checks: antenna, density etc), ERC, LVL (GDS
compare).

Post-layout verification refers usually to the extracted circuit simulations.

-r.


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