Re: gEDA-user: Power (and other non-graphical) pins

[Joerg <joergsch@xxxxxxxxxxxxxxxxxxxxx>]

r wrote:
> On Tue, Jan 13, 2009 at 8:47 PM, Joerg <joergsch@xxxxxxxxxxxxxxxxxxxxx> wrote:
>> The backplanes in our ultrasound systems are
>> usually north of 4000 pins and I have never seen a case where there was
>> not a schematic for that.
> 
> In analog IC design it's fairly easy to get schematics even bigger
> than this - that's what you get when you extract the layout. Sure,
> transistor level netlist would do fine for simulation but it is simply
> convenient to have an extracted schematic of the cell (if only for
> netlisting, DRC checks, manually finding some internal devices/nodes).
> 

Yes, because you guys don't have to pay 2-3c for each additional 
transistor or 5c per FET :-)


>> Ok, if gEDA is geared towards ASIC/FPGA that's different. Then it sure
>> won't be my kind of tool, just like BAE isn't (had tried it out lately).
> 
> Believe it or not, gEDA actually strongly focuses on the PCB flow.
> Just look at the symbol attributes - pin numbers, footprints, even
> reference designators come in PCB flavor. There is only partial
> support for the design hierarchy, partial support for libraries,
> partial support for other types of design data (RTL, netlists), no
> functional netlisters, no DRC checks on the design. These issues can
> often be "fixed" using external tools (makefiles, own netlisters and
> rule checkers) but they are enough to discourage most designers from
> even trying the tool. To be honest, looking at the traffic on this
> list, I thought the PCB flow support is fairly decent (or the only one
> that works, for that matter).
> 
> BTW, analog IC guys long since have given up using implicit power
> connections and multi-slot symbols. People simply draw all the power
> lines just like any other wires (sometimes even explicitly modeling
> them with L/R/C circuits). Same with the cells (symbols in the PCB
> world) - the closer the symbol is to its
> schematic/RTL/layout/extracted view, the better, if only for LVS-ing
> the design or juggling with schematic/extracted views in simulations -
> multiple slots only add unnecessary complexity to the design. Such
> schematics are perhaps a bit more difficult to understand but easier
> to work with.
> 

Same with us discrete circuit and RF designers. We rarely use inherent 
supply pins. Now that RF and digital heads for the GHz ranges that area 
will soon face similar challenges.

In a chip you are right, inherent would be almost impossible because 
every connection is a resistor/inductor. Even the substrate is. On one 
of the HV chips I designed we drove it so far that the fab guys said 
"But it'll electromigrate itself to death in less than a year" ... "It 
only has to live a couple of hours" ... "Oh".

-- 
Regards, Joerg

http://www.analogconsultants.com/



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