Re: gEDA-user: Power (and other non-graphical) pins

[John Doty <jpd@xxxxxxxxx>]

On Jan 13, 2009, at 1:47 PM, Joerg wrote:

> John Doty wrote:
>>
> Then we are working in different worlds.

And that is my point. gEDA has to be flexible to accommodate the  
needs of different worlds, rather than some specific narrow channel.

> But at least we both worked
> with CCD imagers :-)

Since 1974. Still do (ASTRO-H, TESS).

>
>
>>> In design reviews,
>>
>> The schematics are only part of the story. In a NASA design review,
>> the majority of the reviewers won't even look at them.
>>
>
> Last one I saw was mostly schematics and mechanical CAD.

Then you saw only part of the process. Many reviewers are just going  
to look at requirements and specifications. But the real holy of  
holies to NASA is the parts list: there will be no mercy for those  
whose choice of parts is deemed blasphemous.

>
>
>>> for the
>>> TUEV inspector, and so on. They do not want to have to thumb through
>>> reams of paper to find which net something invisible is connected  
>>> to.
>>
>> A schematic of a 2000 pin backplane is pretty useless, while the same
>> data in a human-friendly tabular form makes it really easy to find
>> where to put the scope probe.
>>
>
> Sure, but I don't think that's what gEDA was meant to do.

This is *exactly* what gEDA is intended to do. "Electronic design  
automation", with the emphasis on the "automation". gEDA is a toolkit  
for automating as much of the process as possible.

> That's what
> Excel or OpenOffice is for.

Those are not tools for an automated flow: you can't easily combine  
them with other tools in a scripted fashion. For an automated flow,  
you want automation-friendly tools: awk, perl, troff, TeX, etc. The  
key gEDA tool here is gnetlist, which can do far more than make  
netlists.

> The backplanes in our ultrasound systems are
> usually north of 4000 pins and I have never seen a case where there  
> was
> not a schematic for that.

The existence of the schematic doesn't matter. It's the use. What  
good is such a schematic? For review, revision, or debugging I'd much  
rather have a table: all the information without the eyestrain. But  
with my table-to-pseudo-schematic script and gEDA, I'm free to make a  
schematic or not, as I choose. I can even mix approaches for  
different parts of a board.

>>
>>
>> But those are relevant. My biggest use of gEDA is mixed-signal ASIC
>> design.
>>
>
> Ok, if gEDA is geared towards ASIC/FPGA that's different.

It's not geared toward anything specific. I'm sure ASIC design is a  
minority use. gEDA is *flexible*.

> Then it sure
> won't be my kind of tool, just like BAE isn't (had tried it out  
> lately).

It's a toolkit, not a tool.

>>
>>
>>> They all work the
>>> same way I do, in the graphical domain all the way up to the end  
>>> when
>>> the netlist for the layouter is generated.
>>
>> That approach doesn't scale efficiently to big projects. Graphics are
>> superb for expressing circuit topology at moderate scales. But nobody
>> will ever comprehend how a Pentium works from schematics.
>>
>
> True. That would be ASIC type work.

But mixed-signal boards are now getting to the complexity levels  
where schematics cease to be useful. 200 cm^2 of 0402's and IC's with  
0.5 mm pins is an awful lot of stuff. gEDA gives me the tools to  
achieve the automation leverage to cope here. And I need plenty:  
there's only one of me, and electronic design is only part of what I do.

>
>
>> The Veriog-AMS fans think they can eliminate schematics completely,
>> design analog in code, and have the computer synthesize the netlist
>> from that. That's also a nutty position, but they have a good reason:
>> code scales better than graphics. So, if you want to do really big
>> mixed-signal systems efficiently, you're going to need to do the
>> higher levels with code. The nuttiness comes from thinking one kind
>> of tool should work on all scales.
>>
>> So, a correlated double sampler circuit is best expressed as a
>> schematic, but the higher levels of a system containing 96 such
>> circuits along with a bunch of other stuff is not. At some point,
>> your eyes can't take it all in, so you might as well start making  
>> lists.
>>
>
> That's where the hierarchy comes in, and AFAICT gEDA handles a  
> hierarchy
> nicely.

True.

> You don't see all those 96 identical circuits, just one plus the
> fact that there are 96 of them. I've done a lot of those (in
> schematics), the biggest one 128.

But the problem comes when you get to the upper levels of the  
hierarchy. When you just have boxes connected by busses, the  
topological significance of the graphics is lost. For my ASIC work, I  
find it easier to check the top level schematics by reading the SPICE  
netlists. So, I have to ask myself, what good is such a schematic?  
I'm doing connectors with lists instead of drawings in one current  
project, but maybe I should start doing lists for top level, too.

Of course this isn't a new idea: the digital folks figured this out  
half a century ago. Ever see the design docs for a Minuteman I ICBM  
guidance computer?

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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