gEDA-user: Re: iverilog: Parameters of Parameters

[Stephen Williams <steve@icarus.com>]

lingwitt-Bdlq13kUjeyLZ21kGMrzwg@public.gmane.org wrote:
> In any case, as I stated in my last email,
> this feature probably isn't good to add,
> strictly because it seems to be nonstandard.
> 
> However, the lack of such a feature shows
> the poor thought of Verilog's designers.
> 
> The burden is on the programmer, not
> the tools.

This is a bit too glib for my tastes. Parameters, parameter overrides
and constraints on parameters were thoroughly debated during the
standardization process, so I don't think it's quite fair for you
to assume you know so much more (or are so much smarter then) the
people who were there.

In this case, they did a reasonable job of keeping the problem
under control. The cycles that remain can be detected by simple
graph algorithms, are localized, and are easy to point out to a
user. Currently, even though dependencies can span heirarchy, the
cycles are guaranteed to be localized within a module instance.
If cycles were allowed to span heirarchy up and down then you
can have the impossible situation of cycles wrapped all around
your design. Add generates to that and you can have an unstable,
non-repeating "cycle".

As you can tell, I've thought about this some by now, and I now
think it would indeed be a bad feature:-P

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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