Re: gEDA-user: gnetlist (was: Perl)

[DJ Delorie <dj@xxxxxxxxxxx>]

One thought I had for gnetlist backends, is to recode gnetlist as a
set of libraries.  The Core would only load the design files
(schematics, spreadsheets, databases, back-annotation info, etc) as
raw data; the backend would be required to call at least one library
function that said "I want data in this format".  The "formats" could
be layered in the library, with each layer distilling the data even
further, so that each backend could choose how much the data is
pre-digested.

Something like PCB's current backend, for example, would ask for a
fully flattened design with all connectivity resolved and reduced to
pin-level netlists.  A Verilog backend might want busses not reduced
to pin-level, or the heirarchy left intact.  A BOM might not bother
with connectivity, but ask for additional attribute processing.  Etc.

This way, we can centralize a lot of the common tasks, without forcing
those decisions on the backends.


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