Re: gEDA-user: Slotting and visible power connections

[r <nbs.public@xxxxxxxxx>]

On Fri, Nov 7, 2008 at 5:44 PM, Kai-Martin Knaak <kmk@xxxxxxxxxxxxxxx> wrote:
> On Fri, 07 Nov 2008 12:37:30 +0100, Stephan Boettcher wrote:
>
>> Why do you want power symbols?
>
> Analog circuits require dedicated capacitors at the power pins.

I agree.

In analog IC design (this is my field) things went both a bit further
and in slightly different direction. People are partitioning
schematics exactly as they would partition the layout (using a design
hierarchy). This implies that slotted symbols may not be used, even in
situations where it would make sense (e.g. an integrated multichannel
cell). It is not uncommon to model supply or critical signal tracks
explicitly to handle signal integrity issues, supply/ground noise etc.

The main difference from the component-level world is that in the IC
design tools are strongly focused on simulation, both of the
schematics and the layout. Typical designs are also more complex so it
is better not to rely on the layout designer intuition (even if it is
the same person as the circuit designer). Implicit pins are commonly
forbidden. I've even seen guidelines prohibiting implicit net
connections (by named nets) or large flat schematics (say, larger than
an A3 size page).

These problems are slowly drifting to the component-level world.
Slotted devices almost don't exist (except maybe for 74XXX type
devices) and even if they do, it's is still better to instantiate them
explicitly (like using e a single symbol for a 4x opamp). Simulation
becomes a part of the design flow, at least for parts of the system,
as well as does the extraction of the PCB parasitics.

-r.


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