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Re: gEDA-user: VeriWell now on SourceForge

On Tue, Sep 27, 2005 at 03:40:06PM +0000, Hagen Sankowski wrote:
> Hello Karel.
> 
> Am 27.09.2005 10:08:45 schrieb(en) Karel Kulhavy:
> 
> > What is better, Verilog or VHDL?
> 
> There's no answer. Verilog belongs more to real hardware stuff, VHDL belongs more to behavioral simulation stuff. Both HDL have it pros and cons. 
> 
> Doesn't we talk this week about the open weekend in Prague? Send me an
> invitation and I'll held a quite funny lecture about that topic out of
> my 8 years of experience...

I don't have anything common with OpenWeekend Prague so I cannot send
you an invitation. The URL is here:
http://www.openweekend.cz/

I don't live in Prague anymore, now I live in Zurich.

CL<