Re: gEDA-user: First PCB

[andrewm <andrewm@xxxxxxxxxxxxxxx>]

 > John Griessen wrote:
 >
 > I like your minimization of vias.  Most of
 > your vias seem to double as headers for
 > test and interconnect.

The only way I could work out how to do this
easily in PCB was to make a new component
that was just 5 pins in a row and add them
in the schematic to the traces I knew where
going to be the via/test points along the
side.

That is probably the nice way to do it and
makes things more followable.  In protel
I just used to pop down vias and pads where
ever I felt like it and it would let me
connect them.

http://www.thehacktory.com/IR-simple-schem.png

The ones marked as GPIO1..3 are also the
AVRs ISP pins so that I can get the infrared
based bootloader in the chip when they are
first put together.  After that re-flashing
of the chip does not need a connection.

Seeing as it does not add any extra board
space or weight I have left them for use as
GPIO and also added 4 more pads on the other
side to give access to 4 ADC pins in case
anyone wants to use them.

 > Looks good.  Good use of space -- little
 > waste, but not too crammed to be a
 > practical test/eval/modular add-on board.

I was actually cheating a little bit.
This board was a redesign of my last
board I ever made with protel.

http://www.thehacktory.com/Simple-IR-RX-Prototype-V1p4-Bottom.jpg
http://www.thehacktory.com/Simple-IR-RX-Prototype-V1p4-Top.jpg

Protel for DOS used 1/1000th of an inch
as its internal measurements.  Made
aligning things on 0.45mm pads a bit
hard.  So the ATMega48 in the photo is
my reason for switching to PCB/gEDA.

 > PS  What's it look like if you run global
 > puller on it?

It took 10 minutes for the auto opitmizer to
run and all it did was spread out a few of
my manually added teardrops and pulled one
track straight from GND to VCC to create a
dead short.

 > Ben Jackson wrote:
 > If that big square is a thermal pad, it's
 > not going to help much if you don't stitch
 > it to more copper on the other side...

The big square pad under the QFN28_4 is the
extra GND pin for the ATMega48.  The chip is
only going to be pulling 0.5 to 1mA so should
not need extra heatsinking.  It does however
help with noise performance to connect the
pad to GND.

The drain pad on the SC70-6-EP FET is being
used as heat sink.  And before I go into prod.
I may try get more copper and vias around it
for better heat dissipation.  Though I am
being very conservative with that FET.  It is
good for 5.5Amp and it is only going to be
asked to do 0.5 to 1Amp in normal duty.

 > Also, I think your attachments to the sides
 > of those long, skinny pads might cause you
 > grief if you don't have a soldermask.

Yes - will have solder mask and paste stencil.

 > John Griessen wrote:
 > So, what is that "under chip" square
 > of copper connected to two pads?
 > A mini ground plane?

http://www.thehacktory.com/datasheets/gp1us30xp_e.pdf

Is the device.  A 38KHz infrared receiver.
The manufacturer recomends the GND pad
underneath to help with noise performance.
Coupled with the metal case on the top it
forms a cage/box around the whole thing.

I agree with the manufacture in this case.
The receiver is very very sensitive to noise
and you can gain/loose meters of range with
out the GND.  Careful placement of other
noise on the boards and snuffing them can
gain/loose you 10 meters range.




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