Re: gEDA-user: terminators

[Steven Michalske <smichalske@xxxxxxxxx>]

On Apr 6, 2009, at 7:03 PM, DJ Delorie wrote:

>
>> longest clock Vs. shortest data and vice versa.
>>
>> You want your data eye to be nice and big, the sampling clock right
>> in the middle of it.  The cleaner the eye the slower your edge rates
>> can go.
>
> So, long story short... I need to redesign the board :-(
>
> I tried adding serpentines but there isn't enough room to add more
> than an inch or so, leaving another inch of mismatch.  If I reroute
> the signals under the chip instead of around it, I can save an inch or
> more, then serpentine the rest to match trace lengths.
>
>

did you do the math?

an inch is 170ps of mismatch.....

133MHz is 7.518 ns period

so 2.2% error.  how good are your memories?



if this were say 1033MHz DDR ram modules, you would be hosed.

1.033 GHz is 968ps period
1 inch is 17.6%
Its DDR so..... 2x
35% error  that's toast.   but north bridges have tricks up their  
sleeve they adjust delays in the output and inputs to the ram banks to  
compensate.

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