Re: gEDA-user: Error message when creating a SUBCKT

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Sat, 2008-08-16 at 15:59 -0400, John Doty wrote:
> On Aug 16, 2008, at 3:32 PM, John Doty wrote:
> 
> > Hmm, I wonder if the problem is the hidden power pins,
> 
> I note that it there is no mechanism to tell gnetlist what subcircuit  
> pin a hidden net should attach to.

You are correct. Remove the hidden power pins, and the warnings go away.
A little debugging code I added to gnetlist confirmed that these pins
are being passed as "unknown" into the C function behind "get-nets".

The netlist output is "correct" (by some definition of correct) though,
in both cases. However.. perhaps your model for that gate wants power
pins passing to it...

Best make up a custom symbol.

> Again, it is strange to use a symbol designed for slotted printed  
> circuit layout in a SPICE simulation.

+1.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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