Re: gEDA-user: discussion on what busses *mean*

[DJ Delorie <dj@xxxxxxxxxxx>]

> D[15:0],A[1:16] with a branch called A[1:16]

I was thinking "the above renames the wires" but perhaps that's a bad
idea.  Yeah, I guess it would have to create a bundle of 32 wires.

No reason you couldn't attach some random attribute to the bus that's
just to give it a mnemonic name :-)

> When I say modules, I'm thinking in verilog, where a port
> corresponds to a "pin", and a port can be multiwire.  Or, you could
> define pin as single wire and create a new thing called a port, that
> has multiwire function.

I'm worried about pcb, though, where pin == physical pin, so not only
do we need to have a bus connect to a symbol, but we have to keep
track of the pin numbers somehow, and still allow for pin swapping via
back annotation and slotting.  Which means *someone* will be
constantly breaking apart busses and putting them back together again.


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user