DJ Delorie wrote: >> JG wrote:
When I say modules, I'm thinking in verilog, where a port corresponds to a "pin", and a port can be multiwire. Or, you could define pin as single wire and create a new thing called a port, that has multiwire function.I'm worried about pcb, though, where pin == physical pin, so not only do we need to have a bus connect to a symbol, but we have to keep track of the pin numbers somehow, and still allow for pin swapping via back annotation and slotting. Which means *someone* will be constantly breaking apart busses and putting them back together again.
Packages with their fixed pin orders add another constraint beyond netnames for busses. Does a bus as we think of it need to be a row of traces in order with no vias jumping over wires to rearrange? I think giving that another name will help talking about it. To me, a bus is conceptually related, but not necessarily "in row order" . In other words, D[0:7] need not be arranged as D[0],D[1],D[2] in physical order. Pin swapping is motivated by wanting to have neat marching rows of traces so they take up the least space. You can get that without having to keep wires in physical number order though. Usually they would be in order, but it should not be a constraint. If I had to change 6 places in a schematic to get D[0],D[1],D[2] in physical order, but just two places to get D[0],D[2],D[1] in physical order, I'd let it be out of physical/number order. John _______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user