Re: gEDA-user: Random thoughts on the future interface of PCB

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Tue, 2010-12-14 at 22:57 +0100, Martin Kupec wrote:

> 	Sometimes, when you place to lines too close, but not that close
> 	in polygon. It will make thin line in the polygon connecting two
> 	part of the polygon. DRC will mark this line as too thin.

Actually, I'm pretty sure the DRC will miss this error (unless the thin
line was _required_ for some connectivity), - And even then I'm not 100%
sure.

>  It
> 	should automaticly erase such lines. Any proposal, how to fix
> 	this?

It is quite a hard problem to solve actually.. I'll have a think about
it... it really needs solving, and I've been looking at / thinking about
polygons recently.

> 	When you make a via in polygon. Change the clerance to too
> 	small value and add thermal(even full thermal). DRC will mark
> 	this via as having too smal clearance. This seems like bug to
> 	me.

Sounds like ;) (I'll point you at a bug tracker to file it at some
point, but we're probably going to move trackers pretty soon anyway, so
you might have the honour of filing the first (new) bug in the new bug
tracker if you wait a while!).

> 	Bigger issues is that when I drag component, lines are dragged
> 	with it. This is fine, but the lines do not respect any
> 	orthogonal/45 deg rules.

You can switch off rubber-band mode in the settings menu. More
intelligent rubber-banding could be done in the future, but is not
trivial to implement.

> 	I cannot simply unmask part of the board. I know how to do it,
> 	but that is not optimal. Having some Solder mask layer with
> 	polygons clearing solder mask would be neat.

Future TODO item for when we re-work layer support in (some) future PCB
version. I'd expect it will not happen any time soon.

> 	And one question. Is it possible to enable snapping to end of
> 	lines? I know about snapping to pins/pads/vias, but have not
> 	found how to snap to end of line.

Hmm, not sure. I thought it worked, but then I've been using my PCB+GL
branch for _ages_, and I fixed up the snapping code there to be more
usable.

> 	This list is just what we came into when trying PCB.
> 	I am definetly not blaming anyone for any of those issuses.
> 	Just letting you know what are my problems.

Thanks for the list.

PS. did I point you at my PCB+GL branch yet?

git://repo.or.cz/geda-pcb/pcjc2.git
("pcb+gl" branch), OR "pcb+gl_experimental".

For me, my biggest bugbear with stock PCB was the lack of layer
translucency, and slow rendering.. so I did this:

http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-6.png
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-2.png


Best wishes,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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