Stephan Boettcher wrote:
This is obviousely wrong, if you layout a copper trace between two net-compatiblekai-martin knaak <kmk@xxxxxxxxxxxxxxx> writes:Bob Paddock wrote:This is a DRC issue. The rules should allow any net to connect to no-net copper. No need to restructure the way pcb handles connectivity.If different nets connect to the same no-net copper there is a short between nets.Of course, connectivity needs to be recalculated (automatically) after a net has been connected to a no-net. As a consequence, theno-net copper will have been converted to what ever net it was connected to.Maybe it is important to recognise, that DRC and LVS are completely orthogonal in PCB, and I think that is a good property, that should be kept. DRC (DesignRule Check) does not consider the netlist.
pads/pins in one go vs. routing to a wrong pin.
The problem is, that all copper patches not connected to a know net are considered to be on different nets - that is a completely arbitrar design choice and in no wayIt checks the connectivity of all copper, and verifies the rules for connected and not-connected copper.
supperior to treating them as on the one "unknown" net.
How do you do that, without testing individual line/arc elements for overlap -LVS (Layout vs Schematic) checks that the copper connections between pins matches the netlist, without checking for DRC rules.
which is a DRC matter ?
As far as I can judge, there is no such separation - there's just datastructures,Distinguishing between net and no-net copper will break this separation. This should not be done lightly.
that don't support net-attributes for lines etc. _______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user