Re: gEDA-user: Insufficient clearance of pad inside polygon

[Karel Kulhavy <clock@xxxxxxxxxxxxx>]

On Wed, Jan 04, 2006 at 11:25:27AM -0500, DJ Delorie wrote:
> 
> > Where is the button for drawing the schematic for me in the first place?
> 
> :-)
> 
> However, his request makes sense.  I didn't disagree with that part, I
> was just asking if a simpler/faster solution would be an acceptable
> compromise.

No - simpler/faster solutions result in gentoo syndrome. While in
Windows to upgrade the system you need to click one button, in gentoo
you need to type about 20 complicated poorly docummented commands. And
when you make a mistake in one of them, do them in improper sequence
(which isn't also documented properly) or god save you gentoo will have
problems with them (for gentoo usually the step the compilation error),
your system will be screwed up and possibly destroyed.

In PCB it's already similar - when you run all optimizations at once,
you usually get a segfault and lost work. So there are manual
optimizations and you need to run them one after another, you don't know
in which sequence, and save the PCB after each of them.

I would rather have one DRC and not a million sub-DRC's and also one
optimization and not a million suboptimizations.

KISS <- keep it simple, stupid! (I still don't know if stupid is a name
given to the target of this message or if it's meant that you should
keep it stupid).

CL<
> 
> Consider spell checkers, for example.  They *all* offer fix-on-the-fly
> of various sorts, and I think PCB should offer something similar.
> It's a *real* pain to keep track of what needs to be fixed, and go
> back and fix them.  Either a fix-on-the-fly feature needs to be added,
> or a DRC layer or overlay needs to be added which tags all the errors
> and lets you remove tags as you fix stuff.
> 
> But making arbitrary changes from inside DRC is harder than an
> independent option that fixes one type of reasonably safe DRC problem.